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? 2010 freescale semiconductor, inc. all rights reserved. freescale semiconductor technical data the mpc8560 integrates a processor core built on power architecture? technology with system logic required for networking, telecommunications, and wireless infrastructure applications. the mpc8560 is a member of the powerquicc iii family of devices that combine system-level support for industry-standard interfaces with processors that implement the embedded category of the power architecture technology. for functional characteristics of the processor, see the mpc8560 powerquicc iii integrated communications processor reference manual . to locate any published errata or updates for this document, contact your freescale sales office. contents 1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 8 3. power characteristics . . . . . . . . . . . . . . . . . . . . . . . . 13 4. clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5. reset initialization . . . . . . . . . . . . . . . . . . . . . . . . . 17 6. ddr sdram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7. ethernet: three-speed, mii management . . . . . . . . 22 8. local bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9. cpm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10. jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11. i2c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12. pci/pci-x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 13. rapidio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 14. package and pin listings . . . . . . . . . . . . . . . . . . . . . 69 15. clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 16. thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 17. system design information . . . . . . . . . . . . . . . . . . . 91 18. device nomenclature . . . . . . . . . . . . . . . . . . . . . . . . 98 19. document revision history . . . . . . . . . . . . . . . . . . . 99 mpc8560 integrated processor hardware specifications document number: mpc8560ec rev. 5, 05/2010
mpc8560 integrated processor hardware specifications, rev. 5 2 freescale semiconductor overview 1overview the following section provides a high-level overview of the device features. figure 1 shows the major functional units within the mpc8560. figure 1. mpc8560 block diagram 1.1 key features the following lists an overview of the mpc8560 feature set: ? high-performance, 32-bit book e?enhanced core that implements the power architecture ? 32-kbyte l1 instruction cache and 32-kbyte l1 data cache with parity protection. caches can be locked entirely or on a per-line basis. separate locking for instructions and data ? memory management unit (mmu) especia lly designed for embedded applications ? enhanced hardware and software debug support ? performance monitor facility (similar to but di fferent from the device performance monitor described in chapter 18, ?performance monitor.? ? high-performance risc cpm operating at up to 333 mhz ? cpm software compatibility with previous powerquicc families ? one instruction per clock i 2 c controller local bus controller rapidio controller pci controller dma controller 10/100/1000 mac 10/100/1000 mac mii, gmii, tbi, rtbi, rgmiis serial dma rom i-memory dpram risc engine parallel i/o baud rate generators timers mcc mcc fcc fcc fcc scc scc scc scc spi i2c tc - layer time slot assigner time slot assigner serial interfaces utopias miis, tdms i/os cpm ddr sdram controller cpm controller interrupt 256-kbyte l2-cache/ sram e500 core 32-kbyte l1 i cache 32-kbyte l1 d cache core complex bus e500 coherency module ocean 16 gb/s rapidio-8 133 mhz pci 64b irqs sdram ddr gpio 32b programmable interrupt controller mphy rmiis
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 3 overview ? executes code from intern al rom or instruction ram ? 32-bit risc architecture ? tuned for communication environments: instruction set supports crc computation and bit manipulation. ? internal timer ? interfaces with the embedded e500 core processor through a 32-kbyte dual-port ram and virtual dma channels for each peripheral controller ? handles serial protocols and virtual dma. ? three full-duplex fast serial communications controllers (fccs) that support the following protocols: ? atm protocol through utopia interface (fcc1 and fcc2 only) ? ieee std 802.3?/fast ethernet ? hdlc ? totally transparent operation ? two multi-channel controllers (mccs) that together can handle up to 256 hdlc/transparent channels at 64 kbps each, multiplexed on up to 8 tdm interfaces ? four full-duplex serial communications controllers (sccs) that support the following protocols: ? high level/synchronous data link control (hdlc/sdlc) ? localtalk (hdlc-based local area network protocol) ? universal asynchronous receiver transmitter (uart) ? synchronous uart (1x clock mode) ? binary synchronous communication (bisync) ? totally transparent operation ? serial peripheral interface (spi) support for master or slave ?i 2 c bus controller ? time-slot assigner supports multiplexing of data from any of the sccs and fccs onto eight time-division multiplexed (tdm) interfaces. the time-slot assigner supports the following tdm formats: ? t1/cept lines ?t3/e3 ? pulse code modulation (pcm) highway interface ? isdn primary rate ? freescale interchip digital link (idl) ? general circuit interface (gci) ? user-defined interfaces ? eight independent baud rate generators (brgs) ? four general-purpose 16-bit timers or two 32-bit timers
mpc8560 integrated processor hardware specifications, rev. 5 4 freescale semiconductor overview ? general-purpose parallel ports?16 parallel i/o lines with interrupt capability ? supports inverse muxing of atm cells (ima) ? 256 kbyte l2 cache/sram ? can be configured as follows ? full cache mode (256-kbyte cache). ? full memory-mapped sram mode (256-k byte sram mapped as a single 256-kbyte block or two 128-kbyte blocks) ? half sram and half cache mode (128- kbyte cache and 128-kbyte memory-mapped sram) ? full ecc support on 64-bit boundary in both cache and sram modes ? cache mode supports instruction caching, data caching, or both ? external masters can force data to be allo cated into the cache through programmed memory ranges or special transaction types (stashing) ? eight-way set-associative cache organization (1024 sets of 32-byte cache lines) ? supports locking the entire cache or selected lines. individual line locks are set and cleared through book e instructions or by externally mastered transactions ? global locking and flash clearing done through writes to l2 configuration registers ? instruction and data locks can be flash cleared separately ? read and write buffering for internal bus accesses ? sram features include the following: ? i/o devices access sram regions by marking transactions as snoopable (global) ? regions can reside at any ali gned location in the memory map ? byte accessible ecc is protected using read-modify-write transactions accesses for smaller than cache-line accesses. ? address translation and mapping unit (atmu) ? eight local access windows define mapping within local 32-bit address space ? inbound and outbound atmus map to larger external address spaces ? three inbound windows plus a configuration window on pci/pci-x ? four inbound windows plus a default and configuration window on rapidio ? four outbound windows plus default translation for pci ? eight outbound windows plus default translation for rapidio ? ddr memory controller ? programmable timing supporting ddr-1 sdram ? 64-bit data interface, up to 333-mhz data rate ? four banks of memory supported, each up to 1 gbyte ? dram chip configurations from 64 mbits to 1 gbit with x8/x16 data ports ? full ecc support ? page mode support (up to 16 simultaneous open pages)
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 5 overview ? contiguous or discontiguous memory mapping ? read-modify-write support for rapidio atomic increment, decrement, set, and clear transactions ? sleep mode support for self refresh sdram ? supports auto refreshing ? on-the-fly power management using cke signal ? registered dimm support ? fast memory access via jtag port ? 2.5-v sstl2 compatible i/o ? rapidio interface unit ? 8-bit rapidio i/o and messaging protocols ? source-synchronous double data rate (ddr) interfaces ? supports small type systems (small domain, 8-bit device id) ? supports four priority levels (ordering within a level) ? reordering across priority levels ? maximum data payload of 256 bytes per packet ? packet pacing support at the physical layer ? crc protection for packets ? supports atomic operations increment, decrement, set, and clear ? lvds signaling ? rapidio?compliant message unit ? one inbound data message structure (inbox) ? one outbound data message structure (outbox) ? supports chaining and direct modes in the outbox ? support of up to 16 packets per message ? support of up to 256 bytes per packet and up to 4 kbytes of data per message ? supports one inbound doorbell message structure ? programmable interrupt controller (pic) ? programming model is compliant with the openpic architecture ? supports 16 programmable interrupt a nd processor task priority levels ? supports 12 discrete external interrupts ? supports 4 message interrupts with 32-bit messages ? supports connection of an external interr upt controller such as the 8259 programmable interrupt controller ? four global high resolution timers/count ers that can generate interrupts ? supports 22 other internal interrupt sources ? supports fully nested interrupt delivery ? interrupts can be routed to external pin for external processing
mpc8560 integrated processor hardware specifications, rev. 5 6 freescale semiconductor overview ? interrupts can be routed to the e500 core ?s standard or critical interrupt inputs ? interrupt summary registers allow fast identification of interrupt source ?i 2 c controller ? two-wire interface ? multiple master support ? master or slave i 2 c mode support ? on-chip digital filtering rejects spikes on the bus ? boot sequencer ? optionally loads configuration data from serial rom at reset via the i 2 c interface ? can be used to initialize configuration registers and/or memory ? supports extended i 2 c addressing mode ? data integrity checked with preamble signature and crc ? local bus controller (lbc) ? multiplexed 32-bit address and data operating at up to 166 mhz ? eight chip selects support eight external slaves ? up to eight-beat burst transfers ? the 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller ? three protocol engines availabl e on a per chip select basis: ? general purpose chip select machine (gpcm) ? three user programmable machines (upms) ? dedicated single data rate sdram controller ? parity support ? default boot rom chip select with configurable bus width (8-,16-, or 32-bit) ? two three-speed (10/100/1gb) ethernet controllers (tsecs) ? dual ieee 802.3, 802.3u, 802.3x, 802.3z, 802.3ac, 802.3ab compliant controllers ? support for different ethernet physical interfaces: ? 10/100/1gb mbps ieee 802.3 gmii ? 10/100 mbps ieee 802.3 mii ? 10 mbps ieee 802.3 mii ? 1000 mbps ieee 802.3z tbi ? 10/100/1gb mbps rgmii/rtbi ? full- and half-duplex support ? buffer descriptors are backward compatible with mpc8260 and mpc860t 10/100 programming models ? 9.6-kbyte jumbo frame support ? rmon statistics support ? 2-kbyte internal transmit and receive fifos
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 7 overview ? mii management interface for control and status ? programmable crc generation and checking ? ability to force allocation of header information and buffer descriptors into l2 cache. ? ocean switch fabric ? four-port crossbar packet switch ? reorders packets from a source based on priorities ? reorders packets to bypass blocked packets ? implements starvation avoidance algorithms ? supports packets with payloads of up to 256 bytes ? integrated dma controller ? four-channel controller ? all channels accessible by both the local and remote masters ? extended dma functions (advanced chaining and striding capability) ? support for scatter and gather transfers ? misaligned transfer capability ? interrupt on completed segment, link, list, and error ? supports transfers to or from any local memory or i/o port ? selectable hardware-enforced coherency (snoop/no-snoop) ? ability to start and flow control each dma channel from external 3-pin interface ? ability to launch dma from single write transaction ? pci/pci-x controller ? pci 2.2 and pci-x 1.0 compatible ? 64- or 32-bit pci port supports at 16 to 66 mhz ? 64-bit pci-x support up to 133 mhz ? host and agent mode support ? 64-bit dual address cycle (dac) support ? pci-x supports multiple split transactions ? supports pci-to-memory and memory-to-pci streaming ? memory prefetching of pci read accesses ? supports posting of processor-to-pci and pci-to-memory writes ? pci 3.3-v compatible ? selectable hardware-enforced coherency ? power management ? fully static 1.2-v cmos design with 3.3- and 2.5-v i/o ? supports power saving modes: doze, nap, and sleep ? employs dynamic power management, which au tomatically minimizes power consumption of blocks when they are idle.
mpc8560 integrated processor hardware specifications, rev. 5 8 freescale semiconductor electrical characteristics ? system performance monitor ? supports eight 32-bit counters that count the occurrence of selected events ? ability to count up to 512 counter-specific events ? supports 64 reference events that can be counted on any of the 8 counters ? supports duration and quantity threshold counting ? burstiness feature that permits counting of burst events with a programmable time between bursts ? triggering and chaining capability ? ability to generate an interrupt on overflow ? system access port ? uses jtag interface and a tap controller to access entire system memory map ? supports 32-bit accesses to configuration registers ? supports cache-line burst accesses to main memory ? supports large block (4-kbyte) uploads and downloads ? supports continuous bit streaming of en tire block for fast upload and download ? ieee std 1149.1?-compliant, jtag boundary scan ? 783 fc-pbga package 2 electrical characteristics this section provides the electrical specifications and thermal characteristics for the device. the mpc8560 is currently targeted to these specifications. some of these specifications are independent of the i/o cell, but are included for a more complete reference. these are not purely i/o buffer design specifications. 2.1 overall dc electrical characteristics this section covers the ratings, conditions, and other characteristics. 2.1.1 absolute maximum ratings table 1 provides the absolute maximum ratings. table 1. absolute maximum ratings 1 characteristic symbol max value unit notes core supply voltage for devices rated at 667 and 833 mhz for devices rated at 1 ghz v dd ?0.3 to 1.32 ?0.3 to 1.43 v? pll supply voltage for devices rated at 667 and 833 mhz for devices rated at 1 ghz av dd ?0.3 to 1.32 ?0.3 to 1.43 v? ddr dram i/o voltage gv dd ?0.3 to 3.63 v ?
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 9 electrical characteristics 2.1.2 power sequencing the mpc8560 requires its power rails to be applied in a specific sequence in order to ensure proper device operation. these requirements are as follows for power up: 1. v dd , av dd 2. gv dd , lv dd , ov dd (i/o supplies) items on the same line have no ordering requirement w ith respect to one another. items on separate lines must be ordered sequentially such that voltage rails on a previous step must reach 90 percent of their value before the voltage rails on the current step reach 10 percent of theirs. note if the items on line 2 must precede items on line 1, ensure that the delay does not exceed 500 ms and the power sequence is not done more than once per day in a production environment. three-speed ethernet i/o voltage lv dd ?0.3 to 3.63 ?0.3 to 2.75 v? cpm, pci/pci-x, local bus, rapidio, 10/100 ethernet, mii management, duart, system control and power management, i 2 c, and jtag i/o voltage ov dd ?0.3 to 3.63 v 3 input voltage ddr dram signals mv in ?0.3 to (gv dd + 0.3) v 2, 5 ddr dram reference mv ref ?0.3 to (gv dd + 0.3) v 2, 5 three-speed ethernet signals lv in ?0.3 to (lv dd + 0.3) v 4, 5 cpm, local bus, rapidio, 10/100 ethernet, sysclk, system control and power management, i 2 c, and jtag signals ov in ?0.3 to (ov dd + 0.3) v 5 pci/pci-x ov in ?0.3 to (ov dd + 0.3) v 6 storage temperature range t stg ?55 to 150 ?c c? notes: 1. functional and tested operating conditions are given in ta b l e 2 . absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. caution: mv in must not exceed gv dd by more than 0.3 v. this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 3. caution: ov in must not exceed ov dd by more than 0.3 v. this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 4. caution: lv in must not exceed lv dd by more than 0.3 v. this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 5. (m,l,o)v in and mv ref may overshoot/undershoot to a voltage and for a maximum duration as shown in figure 2 . 6. ov in on the pci interface may overshoot/undershoot according to the pci electrical specification for 3.3-v operation, as shown in figure 3 . table 1. absolute maximum ratings 1 (continued) characteristic symbol max value unit notes
mpc8560 integrated processor hardware specifications, rev. 5 10 freescale semiconductor electrical characteristics note from a system standpoint, if the i/o power supplies ramp prior to the v dd core supply, the i/os on the device may drive a logic one or zero during power-up. 2.1.3 recommended operating conditions table 2 provides the recommended operating conditions fo r the device. note that the values in table 2 are the recommended and tested operating conditions. prope r device operation outside of these conditions is not guaranteed. table 2. recommended operating conditions characteristic symbol recommended value unit core supply voltage for devices rated at 667 and 833 mhz for devices rated at 1 ghz v dd 1.2 v 60 mv 1.3 v 50 mv v pll supply voltage for devices rated at 667 and 833 mhz for devices rated at 1 ghz av dd 1.2 v 60 mv 1.3 v 50 mv v ddr dram i/o voltage gv dd 2.5 v 125 mv v three-speed ethernet i/o voltage lv dd 3.3 v 165 mv 2.5 v 125 mv v cpm, pci/pci-x, local bus, rapidio, 10/100 ethernet, mii management, duart, system control and power management, i 2 c, and jtag i/o voltage ov dd 3.3 v 165 mv v input voltage ddr dram signals mv in gnd to gv dd v ddr dram reference mv ref gnd to gv dd/2 v three-speed ethernet signals lv in gnd to lv dd v cpm, pci/pci-x, local bus, rapidio, 10/100 ethernet, mii management, duart, sysclk, system control and power management, i 2 c, and jtag signals ov in gnd to ov dd v die-junction temperature t j 0 to 105 c
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 11 electrical characteristics figure 2 shows the undershoot and overshoot voltages at the interfaces of the mpc8560. figure 2. overshoot/undershoot voltage for gv dd /ov dd /lv dd the device core voltage must always be provided at nominal 1.2 v (see table 2 for actual recommended core voltage). voltage to the processor interface i/os are provided through separate sets of supply pins and must be provided at the voltages shown in table 2 . the input voltage threshold scales with respect to the associated i/o supply voltage. ov dd and lv dd based receivers are simple cmos i/o circuits and satisfy appropriate lvcmos type specifications. the ddr sdram interface uses a single-ended differential receiver referenced the externally supplied mv ref signal (nominally set to gv dd /2) as is appropriate for the sstl2 electrical signaling standard. gnd gnd ? 0.3 v gnd ? 0.7 v not to exceed 10% g/l/ov dd + 20% g/l/ov dd g/l/ov dd + 5% of t sys 1 t sys refers to the clock period associated with the sysclk signal. v ih v il note:
mpc8560 integrated processor hardware specifications, rev. 5 12 freescale semiconductor electrical characteristics figure 3 shows the undershoot and overshoot voltage of th e pci interface of the mpc8560 for the 3.3-v signals, respectively. figure 3. maximum ac waveforms on pci interface for 3.3-v signaling 2.1.4 output driver characteristics table 3 provides information on the characteristics of the output driver strengths. the values are preliminary estimates. table 3. output drive capability driver type programmable output impedance ( ) supply voltage notes local bus interface utilities signals 25 ov dd = 3.3 v 1 42 (default) pci signals 25 2 42 (default) ddr signal 20 gv dd = 2.5 v ? cpm pa, pb, pc, and pd signals 42 ov dd = 3.3 v ? tsec/10/100 signals 42 lv dd = 2.5/3.3 v ? duart, system control, i2c, jtag 42 ov dd = 3.3 v ? rapidio n/a (lvds signaling) n/a ? notes: 1. the drive strength of the local bus interface is determined by the configuration of the appropriate bits in porimpscr. 2. the drive strength of the pci interface is determined by the setting of the pci_gnt1 signal at reset. 11 ns (min) over-voltage waveform under-voltage waveform 4 ns (max) 4 ns (max) 62.5 ns ?3.5 v +7.1 v 7.1 v p-to-p (min) 7.1 v p-to-p (min) 0 v +3.6 v
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 13 power characteristics 3 power characteristics the estimated power dissipation on the v dd supply for the mpc8560 is shown in table 4 . the estimated power dissipation on the av dd supplies for the device plls is shown in table 5 . table 4. mpc8560 v dd power dissipation 1,2 ccb frequency (mhz) core frequency (mhz) typical power 3,4 maximum power 5 unit 200 400 5.1 7.7 w 500 5.4 8.0 600 5.8 8.4 267 533 6.0 8.7 w 667 6.4 9.2 800 6.9 10.7 333 667 6.8 9.8 w 833 7.4 11.4 1000 6 11.9 16.5 notes: 1. the values do not include i/o supply power (ov dd , lv dd , gv dd ) or av dd . 2. junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, air flow, power dissipation of other components on the board, and board thermal resistance. any customer design must take these considerations into account to ensure the maximum 105 c junction temperature is not exceeded on this device. 3. typical power is based on a nominal voltage of v dd = 1.2 v, a nominal process, a junction temperature of t j = 105 c, and a dhrystone 2.1 benchmark application. 4. thermal solutions will likely need to design to a number higher than typical power based on the end application, t a target, and i/o power. 5. maximum power is based on a nominal voltage of v dd = 1.2 v, worst case process, a junction temperature of t j = 105 c, and an artificial smoke test. 6. the nominal recommended v dd is 1.3 v for this speed grade. table 5. mpc8560 av dd power dissipation av dd ntypical 1 unit av dd 1 0.007 w av dd 2 0.014 w av dd 3 0.004 w notes: 1. v dd = 1.2 v(1.3 v for 1.0-ghz device), t j = 105c
mpc8560 integrated processor hardware specifications, rev. 5 14 freescale semiconductor power characteristics table 6 provides estimated i/o power numbers for each block: ddr, pci, local bus, rapidio, tsec, and cpm. table 6. estimated typical i/o power consumption interface parameter gv dd (2.5 v) ov dd (3.3 v) lv dd (3.3 v) lv dd (2.5 v) units notes ddr i/o ccb = 200 mhz 0.46 ? ? ? w 1 ccb = 266 mhz 0.59 ? ? ? ccb = 300 mhz 0.66 ? ? ? ccb = 333 mhz 0.73 ? ? ? pci/pci-x i/o 32-bit, 33 mhz ? 0.04 ? ? w 2 32-bit 66 mhz ? 0.07 ? ? 64-bit, 66 mhz ? 0.14 ? ? 64-bit, 133 mhz ? 0.25 ? ? local bus i/o 32-bit, 33 mhz ? 0.07 ? ? w 3 32-bit, 66 mhz ? 0.13 ? ? 32-bit, 133 mhz ? 0.24 ? ? 32-bit, 167 mhz ? 0.30 ? ? rapidio i/o 500 mhz data rate ? 0.96 ? ? w 4 tsec i/o mii ? ? 10 ? mw 5, 6 gmii, tbi (2.5 v) ? ? ? 40 gmii, tbi (3.3 v) ? ? 70 ? rgmii, rtbi ? ? ? 40 cpm-fcc mii ? 15 ? ? mw 7 rmii ? 13 ? ? hdlc 16 mbps ? 9 ? ? utopia-8 sphy ? 60 ? ? utopia-8 mphy ? 100 ? ? utopia-16 sphy ? 94 ? ? utopia-16 mphy ? 135 ? ? cpm-scc hdlc 16 mbps ? 4 ? ? mw 7
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 15 clock timing 4 clock timing 4.1 system clock timing table 7 provides the system clock (sysclk) ac timing specifications for the mpc8560. tdma or tdmb nibble mode ? 10 ? ? mw 7 per channel ? 5 ? ? notes: 1. gv dd =2.5, ecc enabled, 66% bus utilization, 33% write cycles, 10pf load on data, 10pf load on address/command, 10pf load on clock 2. ov dd =3.3, 30pf load per pin, 54% bus utilization, 33% write cycles 3. ov dd =3.3, 25pf load per pin, 5pf load on clock, 40% bus utilization, 33% write cycles 4. v dd =1.2, ov dd =3.3 5. lvdd=2.5/3.3, 15pf load per pin, 25% bus utilization 6. power dissipation for one tsec only 7. ov dd =3.3, 10pf load per pin, 50% bus utilization table 7. sysclk ac timing specifications parameter/condition symbol min typical max unit notes sysclk frequency f sysclk ? ? 166 mhz 1 sysclk cycle time t sysclk 6.0 ? ? ns ? sysclk rise and fall time t kh , t kl 0.6 1.0 1.2 ns 2 sysclk duty cycle t khkl /t sysclk 40 ? 60 % 3 sysclk jitter ? ? ? +/- 150 ps 4, 5 notes: 1. caution: the ccb to sysclk ratio and e500 core to ccb ratio settings must be chosen such that the resulting sysclk frequency, e500 (core) frequency, and ccb frequency do not exceed their respective maximum or minimum operating frequencies. refer to section 15.2, ?platform/system pll ratio ,? and section 15.3, ?e500 core pll ratio ,? for ratio settings. 2. rise and fall times for sysclk are measured at 0.6 v and 2.7 v. 3. timing is guaranteed by design and characterization. 4. this represents the total input jitter?short term and long term?and is guaranteed by design. 5. for spread spectrum clocking, guidelines are +/-1% of the input frequency with a maximum of 60 khz of modulation regardless of the input frequency. table 6. estimated typical i/o power consumption (continued) interface parameter gv dd (2.5 v) ov dd (3.3 v) lv dd (3.3 v) lv dd (2.5 v) units notes
mpc8560 integrated processor hardware specifications, rev. 5 16 freescale semiconductor clock timing 4.2 tsec gigabit reference clock timing table 7 provides the tsec gigabit reference clock (ec_gtx_clk125) ac timing specifications for the mpc8560. 4.3 rapidio transmit clock input timing table 9 provides the rapidio transmit clock input (rio_tx_clk_in) ac timing specifications for the mpc8560. 4.4 real time clock timing table 10 provides the real time clock (rtc) ac timing specifications for the mpc8560. table 8. ec_gtx_clk125 ac timing specifications parameter/condition symbol min typical max unit notes ec_gtx_clk125 frequency f g125 ?125?mhz? ec_gtx_clk125 cycle time t g125 ?8?ns? ec_gtx_clk125 rise and fall time lv dd =2.5 lv dd =3.3 t g125r , t g125f ?? 0.75 1 ns 2 ec_gtx_clk125 duty cycle gmii, tbi rgmii, rtbi t g125h /t g125 45 47 ? 55 53 %1, 3 notes: 1. timing is guaranteed by design and characterization. 2. rise and fall times for ec_gtx_clk125 are measured from 0.5v and 2.0v for lv dd =2.5v, and from 0.6 and 2.7v for lv dd =3.3v. 3. ec_gtx_clk125 is used to generate gtx clock for tsec transmitter with 2% degradation ec_gtx_clk125 duty cycle can be loosened from 47/53% as long as phy device can tolerate the duty cycle generated by gtx_clk of tsec. table 9. rio_tx_clk_in ac timing specifications parameter/condition symbol min typical max unit notes rio_tx_clk_in frequency f rclk 125 ? ? mhz ? rio_tx_clk_in cycle time t rclk ?? 8ns? rio_tx_clk_in duty cycle t rclkh /t rclk 48 ? 52 % 1 notes: 1. requires 100 ppm long term frequency stability. timing is guaranteed by design and characterization. table 10. rtc ac timing specifications parameter/condition symbol min typical max unit notes rtc clock high time t rtch 2 x t ccb_clk ??ns? rtc clock low time t rtcl 2 x t ccb_clk ??ns?
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 17 reset initialization 5 reset initialization this section describes the ac electrical specifications for the reset initialization timing requirements of the device. table 7 provides the reset initialization ac timing specifications for the mpc8560. table 12 provides the pll and dll lock times. 6 ddr sdram this section describes the dc and ac electrical specifications for the ddr sdram interface of the device. table 11. reset initialization timing specifications parameter/condition min max unit notes required assertion time of hreset 100 ? s? minimum assertion time for sreset 512 ? sysclks 1 pll input setup time with stable sysclk before hreset negation 100 ? s? input setup time for por configs (other than pll config) with respect to negation of hreset 4 ? sysclks 1 input hold time for por configs (including pll config) with respect to negation of hreset 2 ? sysclks 1 maximum valid-to-high impedance time for actively driven por configs with respect to negation of hreset ? 5 sysclks 1 notes: 1. sysclk is identical to the pci_clk signal and is the primary clock input for the device. see the mpc8560 powerquicc iii integrated communications processor preliminary reference manual for more details. table 12. pll and dll lock times parameter/condition min max unit notes pll lock times ? 100 s? dll lock times 7680 122,880 ccb clocks 1, 2 notes: 1. dll lock times are a function of the ratio between the output clock and the platform (or ccb) clock. a 2:1 ratio results in t he minimum and an 8:1 ratio results in the maximum. 2. the ccb clock is determined by the sysclk platform pll ratio.
mpc8560 integrated processor hardware specifications, rev. 5 18 freescale semiconductor ddr sdram 6.1 ddr sdram dc electrical characteristics table 13 provides the recommended operating conditions for the ddr sdram component(s) of the mpc8560. table 14 provides the ddr capacitance. 6.2 ddr sdram ac electrical characteristics this section provides the ac electrical characteristics for the ddr sdram interface. table 13. ddr sdram dc electrical characteristics parameter/condition symbol min max unit notes i/o supply voltage gv dd 2.375 2.625 v 1 i/o reference voltage mv ref 0.49 gv dd 0.51 gv dd v2 i/o termination voltage v tt mv ref ? 0.04 mv ref + 0.04 v 3 input high voltage v ih mv ref + 0.18 gv dd + 0.3 v 4 input low voltage v il ?0.3 mv ref ? 0.18 v 4 output leakage current i oz ?10 10 a5 output high current (v out = 1.95 v) i oh ?15.2 ? ma ? output low current (v out = 0.35 v) i ol 15.2 ? ma ? mv ref input leakage current i vref ?100 a? notes: 1. gv dd is expected to be within 50 mv of the dram gv dd at all times. 2. mv ref is expected to be equal to 0.5 gv dd , and to track gv dd dc variations as measured at the receiver. peak-to-peak noise on mv ref may not exceed 2% of the dc value. 3. v tt is not applied directly to the device. it is the supply to which far end signal termination is made and is expected to be equa l to mv ref . this rail should track variations in the dc level of mv ref . 4. v ih can tolerate an overshoot of 1.2v over gv dd for a pulse width of 3 ns, and the pulse width cannot be greater than t mck . v il can tolerate an undershoot of 1.2v below gnd for a pulse width of 3 ns, and the pulse width cannot be greater than t mck . 5. output leakage is measured with all outputs disabled, 0 v v out gv dd . table 14. ddr sdram capacitance parameter/condition symbol min max unit notes input/output capacitance: dq, dqs, msync_in c io 68pf1 delta input/output capacitance: dq, dqs c dio ?0.5pf1 note: 1. this parameter is sampled. gv dd = 2.5 v 0.125 v, f = 1 mhz, t a = 25 c, v out = gv dd /2, v out (peak to peak) = 0.2 v.
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 19 ddr sdram 6.2.1 ddr sdram input ac timing specifications table 15 provides the input ac timing specifications for the ddr sdram interface. figure 4. ddr sdram interface input timing 6.2.2 ddr sdram output ac timing specifications for chip selects mcs1 and mcs2 , there will always be at least 200 ddr memory clocks coming out of self-refresh after an hreset before a precharge occurs. this will not necessarily be the case for chip selects mcs0 and mcs3 . 6.2.2.1 dll enabled mode table 16 and table 17 provide the output ac timing specifications and measurement conditions for the ddr sdram interface with the ddr dll enabled. table 15. ddr sdram input ac timing specifications at recommended operating conditions with gv dd of 2.5 v 5%. parameter symbol min max unit notes ac input low voltage v il ?mv ref ? 0.31 v ? ac input high voltage v ih mv ref + 0.31 gv dd + 0.3 v ? mdqs?mdq/mecc input skew per byte for ddr = 333 mhz for ddr 266 mhz t diskew -750 -1125 750 1125 ps 1, 2 note: 1. maximum possible skew between a data strobe (mdqs[n]) and any corresponding bit of data (mdq[8n + {0...7}] if 0 n 7) or ecc (mecc[{0...7}] if n=8). 2. for timing budget analysis, the device consumes 550 ps of the total budget. table 16. ddr sdram output ac timing specifications?dll mode at recommended operating conditions with gv dd of 2.5 v 5%. parameter symbol 1 min max unit notes mck[n] cycle time, (mck[n]/mck [n] crossing) t mck 610ns2 on chip clock skew t mckskew ? 150 ps 3, 8 mdqs[n] mdq[n] t diskew t diskew
mpc8560 integrated processor hardware specifications, rev. 5 20 freescale semiconductor ddr sdram mck[n] duty cycle t mckh /t mck 45 55 % 8 addr/cmd output valid t ddkhov ?3ns4, 9 addr/cmd output invalid t ddkhox 1?ns4, 9 write cmd to first mdqs capture edge t ddshmh t mck + 1.5 t mck + 4.0 ns 5 mdq/mecc/mdm output setup with respect to mdqs 333 mhz 266 mhz 200 mhz t ddkhds, t ddklds 900 1100 1200 ?ps6, 9 mdq/mecc/mdm output hold with respect to mdqs 333 mhz 266 mhz 200 mhz t ddkhdx, t ddkldx 900 1100 1200 ?ps6, 9 mdqs preamble start t ddshmp 0.75 t mck + 1.5 0.75 t mck + 4.0 ns 7, 8 mdqs epilogue end t ddshme 1.5 4.0 ns 7, 8 notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. output hold time can be read as ddr timing (dd) from the rising or falling edge of the reference clock (kh or kl) until the output went invalid (ox or dx). for example, t ddkhov symbolizes ddr timing (dd) for the time t mck memory clock reference (k) goes from the high (h) state until outputs (o) are valid (v) or output valid time. also, t ddkldx symbolizes ddr timing (dd) for the time t mck memory clock reference (k) goes low (l) until data outputs (d) are invalid (x) or data output hold time. 2. all mck/mck referenced measurements are made from the crossing of the two signals 0.1 v. 3. maximum possible clock skew between a clock mck[n] and its relative inverse clock mck [n], or between a clock mck[n] and a relative clock mck[m] or msync_out. skew measured between complementary signals at gv dd /2. 4. addr/cmd includes all ddr sdram output signals except mck/mck and mdq/mecc/mdm/mdqs. 5. note that t ddshmh follows the symbol conventions described in note 1. for example, t ddshmh describes the ddr timing (dd) from the rising edge of the msync_in clock (sh) until the mdqs signal is valid (mh). t ddshmh can be modified through control of the dqss override bits in the timing_cfg_2 register. these controls allow the relationship between the synchronous clock control timing and the source-synchronous dqs domain to be modified by the user. for best turnaround times, these may need to be set to delay t ddshmh an additional 0.25t mck . this will also affect t ddshmp and t ddshme accordingly. see the mpc8560 powerquicc iii integrated communications processor reference manual for a description and understanding of the timing modifications enabled by use of these bits. 6. determined by maximum possible skew between a data strobe (mdqs) and any corresponding bit of data (mdq), ecc (mecc), or data mask (mdm). the data strobe should be centered inside of the data eye at the pins of the device. 7. all outputs are referenced to the rising edge of msync_in (s) at the pins of the device. note that t ddshmp follows the symbol conventions described in note 1. for example, t ddshmp describes the ddr timing (dd) from the rising edge of the msync_in clock (sh) for the duration of the mdqs signal precharge period (mp). 8. guaranteed by design. 9. guaranteed by characterization. table 16. ddr sdram output ac timing specifications?dll mode (continued) at recommended operating conditions with gv dd of 2.5 v 5%. parameter symbol 1 min max unit notes
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 21 ddr sdram figure 5 provides the ac test load for the ddr bus. figure 5. ddr ac test load figure 6 shows the ddr sdram output timing diagram. figure 6. ddr sdram output timing diagram 6.2.2.2 load effects on address/command bus table 18 provides approximate delay in formation that can be expected for the address and command signals of the ddr controller for various loadings. these numbers are the result of simulations for one topology. the delay numbers will strongly depend on the topology used. these delay numbers show the total delay for the address and command to arrive at the dram devices. the actual delay could be table 17. ddr sdram measurement conditions symbol ddr unit notes v th mv ref 0.31 v v 1 v out 0.5 gv dd v2 notes: 1. data input threshold measurement point. 2. data output measurement point. output gv dd /2 r l = 50 z 0 = 50
mpc8560 integrated processor hardware specifications, rev. 5 22 freescale semiconductor ethernet: three-speed, mii management different than the delays seen in simulation, depending on the system topology. if a heavily loaded system is used, the dll loop may need to be adjusted to meet setup requirements at the dram. 7 ethernet: three-speed, mii management this section provides the ac and dc electrical ch aracteristics for three-speed and mii management. 7.1 three-speed ethernet controller (tsec) (10/100/1gb mbps)?gmii/mii/tbi/rgmii/rtbi electrical characteristics the electrical characteristics specified here apply to all gmii (gigabit media independent interface), mii (media independent interface), tbi (ten-bit inte rface), rgmii (reduced gigabit media independent interface), and rtbi (reduced ten-bit interface) si gnals except mdio (management data input/output) and mdc (management data clock). the rgmii and rtbi interfaces are defined for 2.5 v, while the gmii, mii, and tbi interfaces can be operated at 3.3 or 2.5 v. whether the gmii, mii, or tbi interface is operated at 3.3 or 2.5 v, the timing is compliant with the ieee 802.3 standard. the rgmii and rtbi interfaces follow the hewlett-packard reduced pin-count interface for gigabit ethernet physical layer device specification version 1.2a (9/22/2000). the el ectrical characteristics for mdio and mdc are specified in section 7.3, ?ethernet management interface electrical characteristics.? 7.1.1 tsec dc electrical characteristics all gmii,mii, tbi, rgmii, and rtbi drivers and receivers comply with the dc parametric attributes specified in table 19 and table 20 . the potential applied to the input of a gmii,mii, tbi, rgmii, or rtbi receiver may exceed the potential of the receiver?s power supply (i.e., a gmii driver powered from a 3.6 v supply driving v oh into a gmii receiver powered from a 2.5 v supply). tolerance for dissimilar gmii driver and receiver supply potentials is implicit in these specifications. the rgmii and rtbi signals are based on a 2.5 v cmos interface voltage as defined by jedec eia/jesd8-5. table 18. expected delays for address/command load delay unit 4 devices (12 pf) 3.0 ns 9 devices (27 pf) 3.6 ns 36 devices (108 pf) + 40 pf compensation capacitor 5.0 ns 36 devices (108 pf) + 80 pf compensation capacitor 5.2 ns table 19. gmii, mii, and tbi dc electrical characteristics parameter symbol min max unit supply voltage 3.3 v lv dd 3.13 3.47 v output high voltage (lv dd = min, i oh = ?4.0 ma) v oh 2.40 lv dd + 0.3 v output low voltage (lv dd = min, i ol = 4.0 ma) v ol gnd 0.50 v input high voltage v ih 1.70 lv dd + 0.3 v
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 23 ethernet: three-speed, mii management 7.2 gmii, mii, tbi, rgmii, and rtbi ac timing specifications the ac timing specifications for gmii, mii, tbi, rgmii, and rtbi are presented in this section. 7.2.1 gmii ac timing specifications this section describes the gmii transmit and receive ac timing specifications. 7.2.1.1 gmii transmit ac timing specifications table 21 provides the gmii transmit ac timing specifications. input low voltage v il ?0.3 0.90 v input high current (v in 1 = lv dd )i ih ?40 a input low current (v in 1 = gnd) i il ?600 ? a note: 1. the symbol v in , in this case, represents the lv in symbol referenced in ta b l e 1 and ta b l e 2 . table 20. gmii, mii, rgmii, rtbi, and tbi dc electrical characteristics parameters symbol min max unit supply voltage 2.5 v lv dd 2.37 2.63 v output high voltage (lv dd = min, i oh = ?1.0 ma) v oh 2.00 lv dd + 0.3 v output low voltage (lv dd = min, i ol = 1.0 ma) v ol gnd ? 0.3 0.40 v input high voltage v ih 1.70 lv dd + 0.3 v input low voltage v il ?0.3 0.70 v input high current (v in 1 = lv dd )i ih ?10 a input low current (v in 1 = gnd) i il ?15 ? a note: 1. note that the symbol v in , in this case, represents the lv in symbol referenced in ta ble 1 and ta b l e 2 . table 21. gmii transmit ac timing specifications at recommended operating conditions with lv dd of 3.3 v 5%, or lv dd =2.5v 5%. parameter/condition symbol 1 min typ max unit gtx_clk clock period t gtx ?8.0? ns gtx_clk duty cycle t gtxh /t gtx 40 ? 60 % gmii data txd[7:0], tx_er, tx_en setup time t gtkhdv 2.5 ? ? ns gtx_clk to gmii data txd[7:0], tx_er, tx_en delay t gtkhdx 3 0.5 ? 5.0 ns table 19. gmii, mii, and tbi dc electrical characteristics (continued)
mpc8560 integrated processor hardware specifications, rev. 5 24 freescale semiconductor ethernet: three-speed, mii management figure 7 shows the gmii transmit ac timing diagram. figure 7. gmii transmit ac timing diagram 7.2.1.2 gmii receive ac timing specifications table 22 provides the gmii receive ac timing specifications. gtx_clk data clock rise and fall time t gtxr , t gtxf 2,4 ??1.0ns notes: 1. the symbols used for timing specifications herein follow the pattern t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t gtkhdv symbolizes gmii transmit timing (gt) with respect to the t gtx clock reference (k) going to the high state (h) relative to the time date input signals (d) reaching the valid state (v) to state or setup time. also, t gtkhdx symbolizes gmii transmit timing (gt) with respect to the t gtx clock reference (k) going to the high state (h) relative to the time date input signals (d) going invalid (x) or hold time. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for example, the subscript of t gtx represents the gmii(g) transmit (tx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. signal timings are measured at 0.7 v and 1.9 v voltage levels. 3. guaranteed by characterization. 4. guaranteed by design. table 22. gmii receive ac timing specifications at recommended operating conditions with lv dd of 3.3 v 5%, or lv dd =2.5v 5%. parameter/condition symbol 1 min typ max unit rx_clk clock period t grx ?8.0? ns rx_clk duty cycle t grxh /t grx 40 ? 60 ns rxd[7:0], rx_dv, rx_er setup time to rx_clk t grdvkh 2.0 ? ? ns rxd[7:0], rx_dv, rx_er hold time to rx_clk t grdxkh 0.5 ? ? ns table 21. gmii transmit ac timing specifications (continued) at recommended operating conditions with lv dd of 3.3 v 5%, or lv dd =2.5v 5%. parameter/condition symbol 1 min typ max unit gtx_clk txd[7:0] t gtkhdx t gtx t gtxh t gtxr t gtxf t gtkhdv tx_en tx_er
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 25 ethernet: three-speed, mii management figure 8 provides the ac test load for tsec. figure 8. tsec ac test load figure 9 shows the gmii receive ac timing diagram. figure 9. gmii receive ac timing diagram rx_clk clock rise and fall time t grxr , t grxf 2,3 ??1.0ns note: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t grdvkh symbolizes gmii receive timing (gr) with respect to the time data input signals (d) reaching the valid state (v) relative to the t rx clock reference (k) going to the high state (h) or setup time. also, t grdxkl symbolizes gmii receive timing (gr) with respect to the time data input signals (d) went invalid (x) relative to the t grx clock reference (k) going to the low (l) state or hold time. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for example, the subscript of t grx represents the gmii (g) receive (rx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. signal timings are measured at 0.7 v and 1.9 v voltage levels. 3. guaranteed by design. table 22. gmii receive ac timing specifications (continued) at recommended operating conditions with lv dd of 3.3 v 5%, or lv dd =2.5v 5%. parameter/condition symbol 1 min typ max unit output lv dd /2 r l = 50 z 0 = 50 rx_clk rxd[7:0] t grdxkh t grx t grxh t grxr t grxf t grdvkh rx_dv rx_er
mpc8560 integrated processor hardware specifications, rev. 5 26 freescale semiconductor ethernet: three-speed, mii management 7.2.2 mii ac timing specifications this section describes the mii transmit and receive ac timing specifications. 7.2.2.1 mii transmit ac timing specifications table 23 provides the mii transmit ac timing specifications. figure 10 shows the mii transmit ac timing diagram. figure 10. mii transmit ac timing diagram table 23. mii transmit ac timing specifications at recommended operating conditions with lv dd of 3.3 v 5%, or lv dd =2.5v 5%. parameter/condition symbol 1 min typ max unit tx_clk clock period 10 mbps t mtx 2 ? 400 ? ns tx_clk clock period 100 mbps t mtx ?40?ns tx_clk duty cycle t mtxh/ t mtx 35 ? 65 % tx_clk to mii data txd[3:0], tx_er, tx_en delay t mtkhdx 1515ns tx_clk data clock rise and fall time t mtxr , t mtxf 2,3 1.0 ? 4.0 ns note: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mtkhdx symbolizes mii transmit timing (mt) for the time t mtx clock reference (k) going high (h) until data outputs (d) are invalid (x). note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. for example, the subscript of t mtx represents the mii(m) transmit (tx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. signal timings are measured at 0.7 v and 1.9 v voltage levels. 3. guaranteed by design. tx_clk txd[3:0] t mtkhdx t mtx t mtxh t mtxr t mtxf tx_en tx_er
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 27 ethernet: three-speed, mii management 7.2.2.2 mii receive ac timing specifications table 24 provides the mii receive ac timing specifications. figure 11 shows the mii receive ac timing diagram. figure 11. mii receive ac timing diagram table 24. mii receive ac timing specifications at recommended operating conditions with lv dd of 3.3 v 5%, or lv dd =2.5v 5%. parameter/condition symbol 1 min typ max unit rx_clk clock period 10 mbps t mrx 3 ?400? ns rx_clk clock period 100 mbps t mrx ?40?ns rx_clk duty cycle t mrxh /t mrx 35 ? 65 % rxd[3:0], rx_dv, rx_er setup time to rx_clk t mrdvkh 10.0 ? ? ns rxd[3:0], rx_dv, rx_er hold time to rx_clk t mrdxkh 10.0 ? ? ns rx_clk clock rise and fall time t mrxr , t mrxf 2,3 1.0 ? 4.0 ns note: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mrdvkh symbolizes mii receive timing (mr) with respect to the time data input signals (d) reach the valid state (v) relative to the t mrx clock reference (k) going to the high (h) state or setup time. also, t mrdxkl symbolizes mii receive timing (gr) with respect to the time data input signals (d) went invalid (x) relative to the t mrx clock reference (k) going to the low (l) state or hold time. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for example, the subscript of t mrx represents the mii (m) receive (rx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. signal timings are measured at 0.7 v and 1.9 v voltage levels. 3. guaranteed by design. rx_clk rxd[3:0] t mrdxkh t mrx t mrxh t mrxr t mrxf rx_dv rx_er t mrdvkh valid data
mpc8560 integrated processor hardware specifications, rev. 5 28 freescale semiconductor ethernet: three-speed, mii management 7.2.3 tbi ac timing specifications this section describes the tbi trans mit and receive ac timing specifications. 7.2.3.1 tbi transmit ac timing specifications table 25 provides the tbi transmit ac timing specifications. figure 12 shows the tbi transmit ac timing diagram. figure 12. tbi transmit ac timing diagram table 25. tbi transmit ac timing specifications at recommended operating conditions with lv dd of 3.3 v 5%, or lv dd =2.5v 5%. parameter/condition symbol 1 min typ max unit gtx_clk clock period t ttx ?8.0? ns gtx_clk duty cycle t ttxh /t ttx 40 ? 60 % tcg[9:0] setup time gtx_clk going high t ttkhdv 2.0 ? ? ns tcg[9:0] hold time from gtx_clk going high t ttkhdx 1.0 ? ? ns gtx_clk clock rise and fall time t ttxr , t ttxf 2,3 ??1.0ns notes: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state )(reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t ttkhdv symbolizes the tbi transmit timing (tt) with respect to the time from t ttx (k) going high (h) until the referenced data signals (d) reach the valid state (v) or setup time. also, t ttkhdx symbolizes the tbi transmit timing (tt) with respect to the time from t ttx (k) going high (h) until the referenced data signals (d) reach the invalid state (x) or hold time. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for example, the subscript o f t ttx represents the tbi (t) transmit (tx) clock. for rise and fall times, the latter convention is used with the appropriate letter : r (rise) or f (fall). 2. signal timings are measured at 0.7 v and 1.9 v voltage levels. 3. guaranteed by design. gtx_clk tcg[9:0] t ttx t ttxh t ttxr t ttxf t ttkhdv t ttkhdx
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 29 ethernet: three-speed, mii management 7.2.3.2 tbi receive ac timing specifications table 26 provides the tbi receive ac timing specifications. figure 13 shows the tbi receive ac timing diagram. figure 13. tbi receive ac timing diagram table 26. tbi receive ac timing specifications at recommended operating conditions with lv dd of 3.3 v 5%, or lv dd =2.5v 5%. parameter/condition symbol 1 min typ max unit rx_clk clock period t trx ? 16.0 ? ns rx_clk skew t sktrx 7.5 ? 8.5 ns rx_clk duty cycle t trxh /t trx 40 ? 60 % rcg[9:0] setup time to rising rx_clk t trdvkh 2.5 ? ? ns rcg[9:0] hold time to rising rx_clk t trdxkh 1.5 ? ? ns rx_clk clock rise time and fall time t trxr , t trxf 2,3 0.7 ? 2.4 ns note: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t trdvkh symbolizes tbi receive timing (tr) with respect to the time data input signals (d) reach the valid state (v) relative to the t trx clock reference (k) going to the high (h) state or setup time. also, t trdxkh symbolizes tbi receive timing (tr) with respect to the time data input signals (d) went invalid (x) relative to the t trx clock reference (k) going to the high (h) state. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for example, the subscript of t trx represents the tbi (t) receive (rx) clock. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). for symbols representing skews, the subscript is skew (sk) followed by the clock that is being sk ewed (trx). 2. signal timings are measured at 0.7 v and 1.9 v voltage levels. 3. guaranteed by design. rx_clk1 rcg[9:0] t trx t trxh t trxr t trxf t trdvkh rx_clk0 t trdxkh t trdvkh t trdxkh t sktrx t trxh valid data valid data
mpc8560 integrated processor hardware specifications, rev. 5 30 freescale semiconductor ethernet: three-speed, mii management 7.2.4 rgmii and rtbi ac timing specifications table 27 presents the rgmii and rtbi ac timing specifications. table 27. rgmii and rtbi ac timing specifications at recommended operating conditions with lv dd of 2.5 v 5%. parameter/condition symbol 1 min typ max unit data to clock output skew (at transmitter) t skrgt 5 ?500 0 500 ps data to clock input skew (at receiver) 2 t skrgt 1.0 ? 2.8 ns clock period 3 t rgt 6 7.2 8.0 8.8 ns duty cycle for 1000base-t 4 t rgth /t rgt 6 45 50 55 % duty cycle for 10base-t and 100base-tx 3 t rgth /t rgt 6 40 50 60 % rise and fall time t rgtr , t rgtf 6,7 ? ? 0.75 ns notes: 1. note that, in general, the clock reference symbol representation for this section is based on the symbols rgt to represent rgmii and rtbi timing. for example, the subscript of t rgt represents the tbi (t) receive (rx) clock. note also that the notation for rise (r) and fall (f) times follows the clock symbol that is being represented. for symbols representing skews, th e subscript is skew (sk) followed by the clock that is being skewed (rgt). 2. the rgmii specification requires that pc board designer add 1.5 ns or greater in trace delay to the rx_clk in order to meet this specification. however, as stated above, this device will function with only 1.0 ns of delay. 3. for 10 and 100 mbps, t rgt scales to 400 ns 40 ns and 40 ns 4 ns, respectively. 4. duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long as the minimum duty cycle is not violated and stretching occurs for no more than three t rgt of the lowest speed transitioned between. 5. guaranteed by characterization. 6. guaranteed by design. 7. signal timings are measured at 0.5 v and 2.0 v voltage levels.
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 31 ethernet: three-speed, mii management figure 14 shows the rgmii and rtbi ac timing and multiplexing diagrams. figure 14. rgmii and rtbi ac timing and multiplexing diagrams 7.3 ethernet management interface electrical characteristics the electrical characteristics specified here apply to mii management interface signals mdio (management data input/output) and mdc (management data clock). the electrical characteristics for gmii, rgmii, tbi and rtbi are specified in section 7.1, ?three-speed ethernet controller (tsec) (10/100/1gb mbps)?gmii/mii/tbi/rgmii/rtbi electrical characteristics.? 7.3.1 mii management dc electrical characteristics the mdc and mdio are defined to operate at a supply vo ltage of 3.3 v. the dc electrical characteristics for mdio and mdc are provided in table 28 . table 28. mii management dc electrical characteristics parameter symbol min max unit supply voltage (3.3 v) ov dd 3.13 3.47 v output high voltage (ov dd = min, i oh = ?1.0 ma) v oh 2.10 ov dd + 0.3 v output low voltage (ov dd = min, i ol = 1.0 ma) v ol gnd 0.50 v input high voltage v ih 1.70 ? v input low voltage v il ?0.90 v gtx_clk t rgt t rgth t skrgt tx_ctl txd[8:5] txd[7:4] txd[9] txerr txd[4] txen txd[3:0] (at transmitter) txd[8:5][3:0] txd[7:4][3:0] tx_clk (at phy) rx_ctl rxd[8:5] rxd[7:4] rxd[9] rxerr rxd[4] rxdv rxd[3:0] rxd[8:5][3:0] rxd[7:4][3:0] rx_clk (at phy) t skrgt t skrgt t skrgt
mpc8560 integrated processor hardware specifications, rev. 5 32 freescale semiconductor ethernet: three-speed, mii management 7.3.2 mii management ac electrical specifications table 29 provides the mii management ac timing specifications. input high current (ov dd = max, v in 1 = 2.1 v) i ih ?40 a input low current (ov dd = max, v in = 0.5 v) i il ?600 ? a note: 1. the symbol v in , in this case, represents the ov in symbol referenced in table 1 and ta b l e 2 . table 29. mii management ac timing specifications at recommended operating conditions with ov dd is 3.3 v 5%. parameter/condition symbol 1 min typ max unit notes mdc frequency f mdc 0.893 ? 10.4 mhz 2, 4 mdc period t mdc 96 ? 1120 ns ? mdc clock pulse width high t mdch 32 ? ? ns ? mdc to mdio valid t mdkhdv ? ? 2*[1/(f ccb_clk /8)] ns 3 mdc to mdio delay t mdkhdx 10 ? 2*[1/(f ccb_clk /8)] ns 3 mdio to mdc setup time t mddvkh 5? ?ns? mdio to mdc hold time t mddxkh 0? ?ns? mdc rise time t mdcr ?? 10ns4 mdc fall time t mdhf ?? 10ns4 notes: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t mdkhdx symbolizes management data timing (md) for the time t mdc from clock reference (k) high (h) until data outputs (d) are invalid (x) or data hold time. also, t mddvkh symbolizes management data timing (md) with respect to the time data input signals (d) reach the valid state (v) relative to the t mdc clock reference (k) going to the high (h) state or setup time. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. this parameter is dependent on the ccb clock speed (that is, for a ccb clock of 267 mhz, the maximum frequency is 8.3 mhz and the minimum frequency is 1.2 mhz; for a ccb clock of 333 mhz, the maximum frequency is 10.4 mhz and the minimum frequency is 1.5 mhz). 3. this parameter is dependent on the ccb clock speed (that is, for a ccb clock of 267 mhz, the delay is 60 ns and for a ccb clock of 333 mhz, the delay is 48 ns). 4. guaranteed by design. table 28. mii management dc electrical characteristics (continued) parameter symbol min max unit
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 33 local bus figure 15 shows the mii management ac timing diagram. figure 15. mii management interface timing diagram 8 local bus this section describes the dc and ac electrical sp ecifications for the local bus interface of the device. 8.1 local bus dc electrical characteristics table 30 provides the dc electrical characteristics for the local bus interface. 8.2 local bus ac electrical specifications table 31 describes the general timing parame ters of the local bus interface of the mpc8560 with the dll enabled. table 30. local bus dc electrical characteristics parameter symbol min max unit high-level input voltage v ih 2ov dd + 0.3 v low-level input voltage v il ?0.3 0.8 v input current (v in 1 = 0 v or v in = v dd )i in ?5 a high-level output voltage (ov dd = min, i oh = ?2 ma) v oh ov dd - 0.2 ? v low-level output voltage (ov dd = min, i ol = 2 ma) v ol ?0.2 v note: 1. note that the symbol v in , in this case, represents the ov in symbol referenced in ta b l e 1 and ta b l e 2 . table 31. local bus general timing parameters?dll enabled parameter por configuration symbol 1 min max unit notes local bus cycle time ? t lbk 6.0 ? ns 2 lclk[n] skew to lclk[m] or lsync_out ? t lbkskew ? 150 ps 3, 9 mdc t mddxkh t mdc t mdch t mdcr t mdcf t mddvkh t mdkhdx mdio mdio (input) (output) t mdkhdv
mpc8560 integrated processor hardware specifications, rev. 5 34 freescale semiconductor local bus input setup to local bus clock (except lupwait) ?t lbivkh1 1.8 ? ns 4, 5, 8 lupwait input setup to local bus clock ? t lbivkh2 1.7 ? ns 4, 5 input hold from local bus clock (except lupwait) ?t lbixkh1 0.5 ? ns 4, 5, 8 lupwait input hold from local bus clock ? t lbixkh2 1.0 ? ns 4, 5 lale output transition to lad/ldp output transition (latch hold time) ?t lbotot 1.5 ? ns 6 local bus clock to output valid (except lad/ldp and lale) tsec2_txd[6:5] = 00 t lbkhov1 ? 2.0 ns 4, 8 tsec2_txd[6:5] = 11 (default) 3.5 local bus clock to data valid for lad/ldp tsec2_txd[6:5] = 00 t lbkhov2 ? 2.2 ns 4, 8 tsec2_txd[6:5] = 11 (default) 3.7 local bus clock to address valid for lad tsec2_txd[6:5] = 00 t lbkhov3 ? 2.3 ns 4, 8 tsec2_txd[6:5] = 11 (default) 3.8 local bus clock to lale assertion t lbkhov4 ? 2.3 ns 4, 8 output hold from local bus clock (except lad/ldp and lale) tsec2_txd[6:5] = 00 t lbkhox1 0.7 ? ns 4, 8 tsec2_txd[6:5] = 11 (default) 1.6 output hold from local bus clock for lad/ldp tsec2_txd[6:5] = 00 t lbkhox2 0.7 ? ns 4, 8 tsec2_txd[6:5] = 11 (default) 1.6 local bus clock to output high impedance (except lad/ldp and lale) tsec2_txd[6:5] = 00 t lbkhoz1 ? 2.5 ns 7, 9 tsec2_txd[6:5] = 11 (default) 3.8 table 31. local bus general timing parameters?dll enabled (continued) parameter por configuration symbol 1 min max unit notes
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 35 local bus table 32 describes the general timing parame ters of the local bus interface of the mpc8560 with the dll bypassed. local bus clock to output high impedance for lad/ldp tsec2_txd[6:5] = 00 t lbkhoz2 ? 2.5 ns 7, 9 tsec2_txd[6:5] = 11 (default) 3.8 notes: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t lbixkh1 symbolizes local bus timing (lb) for the input (i) to go invalid (x) with respect to the time the t lbk clock reference (k) goes high (h), in this case for clock one(1). also, t lbkhox symbolizes local bus timing (lb) for the t lbk clock reference (k) to go high (h), with respect to the output (o) going invalid (x) or output hold time. 2. all timings are in reference to lsync_in for dll enabled mode. 3. maximum possible clock skew between a clock lclk[m] and a relative clock lclk[n]. skew measured between complementary signals at ov dd /2. 4. all signals are measured from ov dd /2 of the rising edge of lsync_in for dll enabled to 0.4 ov dd of the signal in question for 3.3-v signaling levels. 5. input timings are measured at the pin. 6. the value of t lbotot is defined as the sum of 1/2 or 1 ccb_clk cycle as programmed by lbcr[ahd], and the number of local bus buffer delays used as programmed at power-on reset with configuration pins tsec2_txd[6:5]. 7. for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 8. guaranteed by characterization. 9. guaranteed by design. table 32. local bus general timing parameters?dll bypassed parameter por configuration symbol 1 min max unit notes local bus cycle time ? t lbk 6.0 ? ns 2 internal launch/capture clock to lclk delay ? t lbkhkt 2.3 3.9 ns 8 lclk[n] skew to lclk[m] or lsync_out ? t lbkskew ? 150 ps 3, 9 input setup to local bus clock (except lupwait) ?t lbivkh1 5.7 ? ns 4, 5 lupwait input setup to local bus clock ? t lbivkh2 5.6 ? ns 4, 5 input hold from local bus clock (except lupwait) ?t lbixkh1 -1.8 ? ns 4, 5 lupwait input hold from local bus clock ? t lbixkh2 -1.3 ? ns 4, 5 lale output transition to lad/ldp output transition (latch hold time) ?t lbotot 1.5 ? ns 6 local bus clock to output valid (except lad/ldp and lale) tsec2_txd[6:5] = 00 t lbklov1 ?-0.3ns 4 tsec2_txd[6:5] = 11 (default) 1.2 table 31. local bus general timing parameters?dll enabled (continued) parameter por configuration symbol 1 min max unit notes
mpc8560 integrated processor hardware specifications, rev. 5 36 freescale semiconductor local bus local bus clock to data valid for lad/ldp tsec2_txd[6:5] = 00 t lbklov2 ?-0.1ns 4 tsec2_txd[6:5] = 11 (default) 1.4 local bus clock to address valid for lad tsec2_txd[6:5] = 00 t lbklov3 ?0ns4 tsec2_txd[6:5] = 11 (default) 1.5 local bus clock to lale assertion t lbkhov4 ?0ns4 output hold from local bus clock (except lad/ldp and lale) tsec2_txd[6:5] = 00 t lbklox1 -3.2 ? ns 4 tsec2_txd[6:5] = 11 (default) -2.3 output hold from local bus clock for lad/ldp tsec2_txd[6:5] = 00 t lbklox2 -3.2 ? ns 4 tsec2_txd[6:5] = 11 (default) -2.3 local bus clock to output high impedance (except lad/ldp and lale) tsec2_txd[6:5] = 00 t lbkloz1 ?0.2ns 7 tsec2_txd[6:5] = 11 (default) 1.5 local bus clock to output high impedance for lad/ldp tsec2_txd[6:5] = 00 t lbkloz2 ?0.2ns 7 tsec2_txd[6:5] = 11 (default) 1.5 notes: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t lbixkh1 symbolizes local bus timing (lb) for the input (i) to go invalid (x) with respect to the time the t lbk clock reference (k) goes high (h), in this case for clock one(1). also, t lbkhox symbolizes local bus timing (lb) for the t lbk clock reference (k) to go high (h), with respect to the output (o) going invalid (x) or output hold time. 2. all timings are in reference to local bus clock for dll bypass mode. timings may be negative with respect to the local bus clock because the actual launch and capture of signals is done with the internal launch/capture clock, which precedes lclk by t lbkhkt . 3. maximum possible clock skew between a clock lclk[m] and a relative clock lclk[n]. skew measured between complementary signals at ov dd /2. 4. all signals are measured from ov dd /2 of the rising edge of local bus clock for dll bypass mode to 0.4 ov dd of the signal in question for 3.3-v signaling levels. 5. input timings are measured at the pin. 6. the value of t lbotot is defined as the sum of 1/2 or 1 ccb_clk cycle as programmed by lbcr[ahd], and the number of local bus buffer delays used as programmed at power-on reset with configuration pins tsec2_txd[6:5]. 7. for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 8. guaranteed by characterization. 9. guaranteed by design. table 32. local bus general timing parameters?dll bypassed (continued) parameter por configuration symbol 1 min max unit notes
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 37 local bus figure 16 provides the ac test load for the local bus. figure 16. local bus ac test load figure 17 through figure 22 show the local bus signals. figure 17. local bus signals, nonspecial signals only (dll enabled) output ov dd /2 r l = 50 z 0 = 50 output signals: la[27:31]/lbctl/lbcke/loe / lsda10/lsdwe/lsdras / lsdcas /lsddqm[0:3] t lbkhov1 t lbkhov2 t lbkhov3 lsync_in input signals: lad[0:31]/ldp[0:3] output (data) signals: lad[0:31]/ldp[0:3] output (address) signal: lad[0:31] lale t lbixkh1 t lbivkh1 t lbivkh2 t lbixkh2 t lbkhox1 t lbkhoz1 t lbkhox2 t lbkhoz2 input signal: lgta t lbotot t lbkhoz2 t lbkhox2 t lbkhov4
mpc8560 integrated processor hardware specifications, rev. 5 38 freescale semiconductor local bus figure 18. local bus signals (dll bypass mode) output signals: la[27:31]/lbctl/lbcke/loe / lsda10/lsdwe/lsdras / lsdcas /lsddqm[0:3] t lbklov2 lclk[n] input signals: lad[0:31]/ldp[0:3] output (data) signals: lad[0:31]/ldp[0:3] lale t lbixkh1 input signal: lgta output (address) signal: lad[0:31] t lbivkh1 t lbixkh2 t lbivkh2 t lbklox1 t lbkloz2 t lbotot internal launch/capture clock t lbklox2 t lbklov1 t lbklov3 t lbkloz1 t lbkhkt t lbklov4
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 39 local bus figure 19. local bus signals, gpcm/upm signals for lccr[clkdiv] = 2 (dll enabled) lsync_in upm mode input signal: lupwait t lbixkh2 t lbivkh2 t lbivkh1 t lbixkh1 t lbkhoz1 t1 t3 input signals: lad[0:31]/ldp[0:3] upm mode output signals: lcs [0:7]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:7]/lwe t lbkhov1 t lbkhov1 t lbkhoz1
mpc8560 integrated processor hardware specifications, rev. 5 40 freescale semiconductor local bus figure 20. local bus signals, gpcm/upm signals for lccr[clkdiv] = 2 (dll bypass mode) internal launch/capture clock upm mode input signal: lupwait t1 t3 input signals: lad[0:31]/ldp[0:3] upm mode output signals: lcs [0:7]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:7]/lwe t lbklov1 t lbkloz1 (dll bypass mode) lclk t lbklox1 t lbivkh2 t lbixkh2 t lbivkh1 t lbixkh1 t lbkhkt
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 41 local bus figure 21. local bus signals, gpcm/upm signals for lccr[clkdiv] = 4 or 8 (dll enabled) lsync_in upm mode input signal: lupwait t lbixkh2 t lbivkh2 t lbivkh1 t lbixkh1 t lbkhoz1 t1 t3 upm mode output signals: lcs [0:7]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:7]/lwe t lbkhov1 t lbkhov1 t lbkhoz1 t2 t4 input signals: lad[0:31]/ldp[0:3] (dll bypass mode)
mpc8560 integrated processor hardware specifications, rev. 5 42 freescale semiconductor cpm figure 22. local bus sign als, gpcm/upm signals for lccr[clkdiv] = 4 or 8 (dll bypass mode) 9cpm this section describes the dc and ac electri cal specifications for the cpm of the mpc8560. 9.1 cpm dc electrical characteristics table 33 provides the dc electrical characteristics for the mpc8560 cpm. table 33. cpm dc electrical characteristics characteristic symbol min max unit notes input high voltage v ih 2.0 3.465 v 1 input low voltage v il gnd 0.8 v 1, 2 output high voltage (i oh = ?8.0 ma) v oh 2.4 ? v 1 output low voltage (i ol = 8.0 ma) v ol ?0.5 v 1 internal launch/capture clock upm mode input signal: lupwait t1 t3 upm mode output signals: lcs [0:7]/lbs [0:3]/lgpl[0:5] gpcm mode output signals: lcs [0:7]/lwe t2 t4 input signals: lad[0:31]/ldp[0:3] (dll bypass mode) lclk t lbklov1 t lbkloz1 t lbklox1 t lbivkh2 t lbixkh2 t lbivkh1 t lbixkh1 t lbkhkt
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 43 cpm 9.2 cpm ac timing specifications table 34 and table 35 provide the cpm input and output ac timing specifications, respectively. output high voltage (i oh = ?2.0 ma) v oh 2.4 ? v 1 output low voltage (i ol = 3.2 ma) v ol ?0.4 v 1 note: 1. this specification applies to the following pins: pa[0?31], pb[4?31], pc[0?31], and pd[4?31]. 2. v il (max) for the iic interface is 0.8 v rather than the 1.5 v specified in the iic standard table 34. cpm input ac timing specifications 1 characteristic symbol 2 min 3 unit fcc inputs?internal clock (nmsi) input setup time t fiivkh 6ns fcc inputs?internal clock (nmsi) hold time t fiixkh 0ns fcc inputs?external clock (nmsi) input setup time t feivkh 2.5 ns fcc inputs?external clock (nmsi) hold time t feixkh b2ns scc/spi inputs?internal clock (nmsi) input setup time t niivkh 6ns scc/spi inputs?internal clock (nmsi) input hold time t niixkh 0ns scc/spi inputs?external clock (nmsi) input setup time t neivkh 4ns scc/spi inputs?external clock (nmsi) input hold time t neixkh 2ns tdm inputs/si?input setup time t tdivkh 4ns tdm inputs/si?hold time t tdixkh 3ns col/crs width high (fcc) t fcch 1.5 clk notes: 1. input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of serial clock. timin gs are measured at the pin. 2. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t fiivkh symbolizes the fcc inputs internal timing (fi) with respect to the time the input signals (i) reaching the valid state (v) relative to the referen ce clock t fcc (k) going to the high (h) state or setup time. and t tdixkh symbolizes the tdm timing (td) with respect to the time the input signals (i) reach the invalid state (x) relative to the reference clock t fcc (k) going to the high (h) state or hold time. 3. pio and timer inputs and outputs are asynchronous to sysclk or any other externally visible clock. pio/timer inputs are internally synchronized to the cpm internal clock. pio/timer outputs should be treated as asynchronous. table 35. cpm output ac timing specifications 1 characteristic symbol 2 min max unit fcc outputs?internal clock (nmsi) delay t fikhox 15.5ns fcc outputs?external clock (nmsi) delay t fekhox 28ns table 33. cpm dc electrical characteristics (continued) characteristic symbol min max unit notes
mpc8560 integrated processor hardware specifications, rev. 5 44 freescale semiconductor cpm figure 16 provides the ac test load for the cpm. figure 23. cpm ac test load figure 24 through figure 29 represent the ac timing from table 34 and table 35 . note that although the specifications generally reference the rising edge of the clock, these ac timing diagrams also apply when the falling edge is the active edge. figure 24 shows the fcc internal clock. figure 24. fcc internal ac timing clock diagram scc/spi outputs?internal clock (nmsi) delay t nikhox 0.5 10 ns scc outputs?external clock (nmsi) delay t nekhox 28ns spi output?external clock (nmsi) delay t sekhox 211ns tdm outputs/si delay t tdkhox 2.5 11 ns notes: 1. output specifications are measured from the 50% level of the rising edge of serial clock to the 50% level of the signal. timi ngs are measured at the pin. 2. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t fikhox symbolizes the fcc inputs internal timing (fi) for the time t fcc memory clock reference (k) goes from the high state (h) until outputs (o) are invalid (x). table 35. cpm output ac timing specifications (continued)1 characteristic symbol 2 min max unit output ov dd /2 r l = 50 z 0 = 50 fcc output signals (when gfmr tci = 1) t fikhox brg_out t fiixkh t fiivkh fcc input signals fcc output signals (when gfmr tci = 0) t fikhox
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 45 cpm figure 25 shows the fcc external clock. figure 25. fcc external ac timing clock diagram figure 26 shows ethernet collision timing on fccs. figure 26. ethernet collision ac timing diagram (fcc) figure 27 shows the scc/spi external clock. figure 27. scc/spi ac timing external clock diagram fcc output signals (when gfmr tci = 1) t fekhox serial clock in t feixkh t feivkh fcc input signals fcc output signals (when gfmr tci = 0) t fekhox col/crs (input) t fcch serial clock in t neixkh t neivkh t nekhox input signals: scc/spi (see note) output signals: scc (see note) note: the clock edge is selectable on scc and spi. t sekhox output signals: spi (see note)
mpc8560 integrated processor hardware specifications, rev. 5 46 freescale semiconductor cpm figure 28 shows the scc/spi internal clock. figure 28. scc/spi ac timing internal clock diagram figure 29 shows tdm input and output signals. figure 29. tdm signal ac timing diagram table 36 shows cpm i 2 c ac timing. table 36. cpm i 2 c ac timing characteristic symbol min max unit scl clock frequency (slave) f scl 0f max 1 hz scl clock frequency (master) f scl brgclk/16512 brgclk/48 hz bus free time between transmissions t sdhdl 1/(2.2 * f scl )? s low period of scl t sclch 1/(2.2 * f scl )? s high period of scl t schcl 1/(2.2 * f scl )? s start condition setup time 2 t schdl 2/(divider * f scl ) ? s start condition hold time 2 t sdlcl 3/(divider * f scl )? s data hold time 2 t scldx 2/(divider * f scl )? s data setup time 2 t sdvch 3/(divider * f scl )? s brg_out t niixkh t nikhox input signals: scc/spi (see note) output signals: scc/spi (see note) note: the clock edge is selectable on scc and spi. t niivkh serial clock in t tdkhox tdm input signals there are 4 possible tdm timing conditions: t tdivkh t tdixkh tdm output signals note: 1. 2. 3. 4. input sampled on the rising edge and output driven on the rising edge (shown). input sampled on the rising edge and output driven on the falling edge. input sampled on the falling edge and output driven on the falling edge. input sampled on the falling edge and output driven on the rising edge.
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 47 cpm figure 30 is a a diagram of cpm i 2 c bus timing. figure 30. cpm i 2 c bus timing diagram table 37 and table 38 are examples of i 2 c ac parameters at i 2 c clock value of 100 khz and 400 khz respectively. sda/scl rise time t srise ? 1/(10 * f scl )s sda/scl fall time t sfall ? 1/(33 * f scl )s stop condition setup time t schdh 2/(divider * f scl ) ? s notes: 1. f max = brgclk/(min_divider*prescaler). where prescaler=25-i2mode[pdiv]; and min_divider=12 if digital filter disabled and 18 if enabled. example #1: if i2mode[pdiv]=11 (prescaler=4) and i2mode[flt]=0 (digital filter disabled) then fmax=brgclk/48 example #2: if i2mode[pdiv]=00 (prescaler=32) and i2mode[flt]=1 (digital filter enabled) then fmax=brgclk/576 2. divider = f scl /prescaler. in master mode: divider = brgclk/(f scl *prescaler) = 2*(i2brg[div]+3) in slave mode: divider = brgclk/(f scl *prescaler) table 37. cpm i 2 c ac timing (f scl = 100 khz) characteristic symbol min max unit scl clock frequency (slave) f scl ? 100 khz scl clock frequency (master) f scl ? 100 khz bus free time between transmissions t sdhdl 4.7 ? s low period of scl t sclch 4.7 ? s high period of scl t schcl 4? s start condition setup time 2 t schdl 2? s start condition hold time 2 t sdlcl 3? s data hold time 2 t scldx 2? s data setup time 2 t sdvch 3? s table 36 . cpm i 2 c ac timing (continued) characteristic symbol min max unit scl sda t sdhdl t sclch t schcl t schdl t sdlcl t scldx t sdvch t srise t sfall t schdh
mpc8560 integrated processor hardware specifications, rev. 5 48 freescale semiconductor cpm sda/scl rise time t srise ?1 s sda/scl fall time t sfall ? 303 ns stop condition setup time t schdh 2? s table 38. cpm i 2 c ac timing (f scl = 400 khz) characteristic symbol min max unit scl clock frequency (slave) f scl ? 400 khz scl clock frequency (master) f scl ? 400 khz bus free time between transmissions t sdhdl 1.2 ? s low period of scl t sclch 1.2 ? s high period of scl t schcl 1? s start condition setup time 2 t schdl 420 ? ns start condition hold time 2 t sdlcl 630 ? ns data hold time 2 t scldx 420 ? ns data setup time 2 t sdvch 630 ? ns sda/scl rise time t srise ? 250 ns sda/scl fall time t sfall ?75ns stop condition setup time t schdh 420 ? ns table 37. cpm i 2 c ac timing (f scl = 100 khz) (continued) characteristic symbol min max unit
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 49 jtag 10 jtag this section describes the ac electrical specificati ons for the ieee 1149.1 (jtag) interface of the device. table 39 provides the jtag ac timing specifications as defined in figure 32 through figure 35 . table 39. jtag ac timing specifications (independent of sysclk) 1 at recommended operating conditions (see ta b l e 2 ). parameter symbol 2 min max unit notes jtag external clock frequency of operation f jtg 0 33.3 mhz ? jtag external clock cycle time t jtg 30 ? ns ? jtag external clock pulse width measured at 1.4 v t jtkhkl 15 ? ns ? jtag external clock rise and fall times t jtgr & t jtgf 02ns6 trst assert time t trst 25 ? ns 3 input setup times: boundary-scan data tms, tdi t jtdvkh t jtivkh 4 0 ? ? ns 4 input hold times: boundary-scan data tms, tdi t jtdxkh t jtixkh 20 25 ? ? ns 4 valid times: boundary-scan data tdo t jtkldv t jtklov 4 4 20 25 ns 5 output hold times: boundary-scan data tdo t jtkldx t jtklox ?ns 5 jtag external clock to output high impedance: boundary-scan data tdo t jtkldz t jtkloz 3 3 19 9 ns 5, 6 notes: 1. all outputs are measured from the midpoint voltage of the falling/rising edge of t tclk to the midpoint of the signal in question. the output timings are measured at the pins. all output timings assume a purely resistive 50- load (see figure 31 ). time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 2. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t jtdvkh symbolizes jtag device timing (jt) with respect to the time data input signals (d) reaching the valid state (v) relative to the t jtg clock reference (k) going to the high (h) state or setup time. also, t jtdxkh symbolizes jtag timing (jt) with respect to the time data input signals (d) went invalid (x) relative to the t jtg clock reference (k) going to the high (h) state. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 3. trst is an asynchronous level sensitive signal. the setup time is for test purposes only. 4. non-jtag signal input timing with respect to t tclk . 5. non-jtag signal output timing with respect to t tclk . 6. guaranteed by design.
mpc8560 integrated processor hardware specifications, rev. 5 50 freescale semiconductor jtag figure 31 provides the ac test load for tdo and the boundary-scan outputs of the device. figure 31. ac test load for the jtag interface figure 32 provides the jtag clock input timing diagram. figure 32. jtag clock input timing diagram figure 33 provides the trst timing diagram. figure 33. trst timing diagram figure 34 provides the boundary-scan timing diagram. figure 34. boundary-scan timing diagram output ov dd /2 r l = 50 z 0 = 50 jtag t jtkhkl t jtgr external clock vm vm vm t jtg t jtgf vm = midpoint voltage (ov dd /2) trst vm = midpoint voltage (ov dd /2) vm vm t trst vm = midpoint voltage (ov dd /2) vm vm t jtdvkh t jtdxkh boundary data outputs boundary data outputs jtag external clock boundary data inputs output data valid t jtkldx t jtkldz t jtkldv input data valid output data valid
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 51 i2c figure 35 provides the test access port timing diagram. figure 35. test access port timing diagram 11 i 2 c this section describes the dc and ac electrical characteristics for the i 2 c interface of the device. 11.1 i 2 c dc electrical characteristics table 40 provides the dc electrical characteristics for the i 2 c interface of the mpc8560. table 40. i 2 c dc electrical characteristics at recommended operating conditions with ov dd of 3.3 v 5%. parameter symbol min max unit notes input high voltage level v ih 0.7 ov dd ov dd + 0.3 v ? input low voltage level v il ?0.3 0.3 ov dd v? low level output voltage v ol 00.2 ov dd v1 pulse width of spikes which must be suppressed by the input filter t i2khkl 050ns2 input current each i/o pin (input voltage is between 0.1 ov dd and 0.9 ov dd (max) i i ?10 10 a3 capacitance for each i/o pin c i ?10pf? notes: 1. output voltage (open drain or open collector) condition = 3 ma sink current. 2. refer to the mpc8560 powerquicc iii integrated communications processor preliminary reference manual for information on the digital filter used. 3. i/o pins will obstruct the sda and scl lines if ov dd is switched off. vm = midpoint voltage (ov dd /2) vm vm t jtivkh t jtixkh jtag external clock output data valid t jtklox t jtkloz t jtklov input data valid output data valid tdi, tms tdo tdo
mpc8560 integrated processor hardware specifications, rev. 5 52 freescale semiconductor i2c 11.2 i 2 c ac electrical specifications table 41 provides the ac timing parameters for the i 2 c interface of the mpc8560. figure 16 provides the ac test load for the i 2 c. figure 36. i 2 c ac test load figure 37 shows the ac timing diagram for the i 2 c bus. table 41. i 2 c ac electrical specifications all values refer to v ih (min) and v il (max) levels (see ta b l e 4 0 ). parameter symbol 1 min max unit scl clock frequency f i2c 0 400 khz low period of the scl clock t i2cl 6 1.3 ? s high period of the scl clock t i2ch 6 0.6 ? s setup time for a repeated start condition t i2svkh 6 0.6 ? s hold time (repeated) start condition (after this period, the first clock pulse is generated) t i2sxkl 6 0.6 ? s data setup time t i2dvkh 6 100 ? ns data hold time: cbus compatible masters i 2 c bus devices t i2dxkl ? 0 2 ? 0.9 3 s set-up time for stop condition t i2pvkh 0.6 ? s bus free time between a stop and start condition t i2khdx 1.3 ? s noise margin at the low level for each connected device (including hysteresis) v nl 0.1 ov dd ?v noise margin at the high level for each connected device (including hysteresis) v nh 0.2 ov dd ?v notes: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t i2dvkh symbolizes i 2 c timing (i2) with respect to the time data input signals (d) reach the valid state (v) relative to the t i2c clock reference (k) going to the high (h) state or setup time. also, t i2sxkl symbolizes i 2 c timing (i2) for the time that the data with respect to the start condition (s) went invalid (x) relative to the t i2c clock reference (k) going to the low (l) state or hold time. also, t i2pvkh symbolizes i 2 c timing (i2) for the time that the data with respect to the stop condition (p) reaching the valid state (v) relative to the t i2c clock reference (k) going to the high (h) state or setup time. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 2. the device provides a hold time of at least 300 ns for the sda signal (referred to the v ihmin of the scl signal) to bridge the undefined region of the falling edge of scl. 3. the maximum t i2dvkh has only to be met if the device does not stretch the low period (t i2cl ) of the scl signal. 4. c b = capacitance of one bus line in pf. 6. guaranteed by design. output ov dd /2 r l = 50 z 0 = 50
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 53 pci/pci-x figure 37. i 2 c bus ac timing diagram 12 pci/pci-x this section describes the dc and ac electrical sp ecifications for the pci/pci-x bus of the device. 12.1 pci/pci-x dc electrical characteristics table 42 provides the dc electrical characteristics for the pci/pci-x interface of the mpc8560. 12.2 pci/pci-x ac electrical specifications this section describes the general ac timing parameters of the pci/pci-x bus of the mpc8560. note that the sysclk signal is used as the pci input clock. table 43 provides the pci ac timing specifications at 66 mhz. table 42. pci/pci-x dc electrical characteristics 1 parameter symbol min max unit high-level input voltage v ih 2ov dd + 0.3 v low-level input voltage v il ?0.3 0.8 v input current (v in 2 = 0 v or v in = v dd ) i in ?5 a high-level output voltage (ov dd = min, i oh = ?100 a) v oh ov dd ? 0.2 ? v low-level output voltage (ov dd = min, i ol = 100 a) v ol ?0.2 v notes: 1. ranges listed do not meet the full range of the dc specifications of the pci 2.2 local bus specifications . 2. note that the symbol v in , in this case, represents the ov in symbol referenced in ta b l e 1 and ta b l e 2 . table 43. pci ac timing specifications at 66 mhz parameter symbol 1 min max unit notes sysclk to output valid t pckhov ?6.0ns2 output hold from sysclk t pckhox 2.0 ? ns 2, 9 sr s sda scl t i2cf t i2sxkl t i2cl t i2ch t i2dxkl t i2dvkh t i2sxkl t i2svkh t i2khkl t i2pvkh t i2cr t i2cf ps
mpc8560 integrated processor hardware specifications, rev. 5 54 freescale semiconductor pci/pci-x sysclk to output high impedance t pckhoz ? 14 ns 2, 3, 10 input setup to sysclk t pcivkh 3.0 ? ns 2, 4, 9 input hold from sysclk t pcixkh 0 ? ns 2, 4, 9 req64 to hreset 9 setup time t pcrvrh 10 t sys ? clocks 5, 6, 10 hreset to req64 hold time t pcrhrx 050ns6, 10 hreset high to first frame assertion t pcrhfv 10 ? clocks 7, 10 notes: 1. note that the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t pcivkh symbolizes pci/pci-x timing (pc) with respect to the time the input signals (i) reach the valid state (v) relative to the sysclk clock, t sys , reference (k) going to the high (h) state or setup time. also, t pcrhfv symbolizes pci/pci-x timing (pc) with respect to the time hard reset (r) went high (h) relative to the frame signal (f) going to the valid (v) state. 2. see the timing measurement conditions in the pci 2.2 local bus specifications . 3. for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 4. input timings are measured at the pin. 5. the timing parameter t sys indicates the minimum and maximum clk cycle times for the various specified frequencies. the system clock period must be kept within the minimum and maximum defined ranges. for values see section 15, ?clocking .? 6. the setup and hold time is with respect to the rising edge of hreset . 7. the timing parameter t pcrhfv is a minimum of 10 clocks rather than the minimum of 5 clocks in the pci 2.2 local bus specifications . 8. the reset assertion timing requirement for hreset is 100 s. 9. guaranteed by characterization. 10.guaranteed by design. table 43. pci ac timing specifications at 66 mhz (continued) parameter symbol 1 min max unit notes
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 55 pci/pci-x figure 16 provides the ac test load for pci and pci-x. figure 38. pci/pci-x ac test load figure 39 shows the pci/pci-x input ac timing conditions. figure 39. pci-pci-x input ac timing measurement conditions figure 40 shows the pci/pci-x output ac timing conditions. figure 40. pci-pci-x output ac timing measurement condition table 44 provides the pci-x ac timing specifications at 66 mhz. table 44. pci-x ac timing specifications at 66 mhz parameter symbol min max unit notes sysclk to signal valid delay t pckhov ? 3.8 ns 1, 2, 3, 7, 8 output hold from sysclk t pckhox 0.7 ? ns 1, 10 sysclk to output high impedance t pckhoz ? 7 ns 1, 4, 8, 11 input setup time to sysclk t pcivkh 1.7 ? ns 3, 5 input hold time from sysclk t pcixkh 0.5 ? ns 10 req64 to hreset setup time t pcrvrh 10 ? clocks 11 hreset to req64 hold time t pcrhrx 050ns11 hreset high to first frame assertion t pcrhfv 10 ? clocks 9, 11 output ov dd /2 r l = 50 z 0 = 50
mpc8560 integrated processor hardware specifications, rev. 5 56 freescale semiconductor pci/pci-x table 45 provides the pci-x ac timing specifications at 133 mhz. pci-x initialization pattern to hreset setup time t pcivrh 10 ? clocks 11 hreset to pci-x initialization pattern hold time t pcrhix 050ns6, 11 notes: 1. see the timing measurement conditions in the pci-x 1.0a specification . 2. minimum times are measured at the package pin (not the test point). maximum times are measured with the test point and load circuit. 3. setup time for point-to-point signals applies to req and gnt only. all other signals are bused. 4. for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 5. setup time applies only when the device is not driving the pin. devices cannot drive and receive signals at the same time. 6. maximum value is also limited by delay to the first transaction (time for hreset high to first configuration access, t pcrhfv ). the pci-x initialization pattern control signals after the rising edge of hreset must be negated no later than two clocks before the first frame and must be floated no later than one clock before frame is asserted. 7. a pci-x device is permitted to have the minimum values shown for t pckhov and t cyc only in pci-x mode. in conventional mode, the device must meet the requirements specified in pci 2.2 for the appropriate clock frequency. 8. device must meet this specification independent of how many outputs switch simultaneously. 9. the timing parameter t pcrhfv is a minimum of 10 clocks rather than the minimum of 5 clocks in the pci-x 1.0a specification. 10.guaranteed by characterization. 11.guaranteed by design. table 45. pci-x ac timing specifications at 133 mhz parameter symbol min max unit notes sysclk to signal valid delay t pckhov ? 3.8 ns 1, 2, 3, 7, 8 output hold from sysclk t pckhox 0.7 ? ns 1, 11 sysclk to output high impedance t pckhoz ? 7 ns 1, 4, 8, 12 input setup time to sysclk t pcivkh 1.4 ? ns 3, 5, 9, 11 input hold time from sysclk t pcixkh 0.5 ? ns 11 req64 to hreset setup time t pcrvrh 10 ? clocks 12 hreset to req64 hold time t pcrhrx 050ns12 hreset high to first frame assertion t pcrhfv 10 ? clocks 10, 12 pci-x initialization pattern to hreset setup time t pcivrh 10 ? clocks 12 table 44. pci-x ac timing specifications at 66 mhz (continued) parameter symbol min max unit notes
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 57 rapidio 13 rapidio this section describes the dc and ac electrical specifications for the rapidio interface of the device. 13.1 rapidio dc electrical characteristics rapidio driver and receiver dc electrical characteristics are provided in table 46 and table 47 , respectively. hreset to pci-x initialization pattern hold time t pcrhix 050ns6, 12 notes: 1. see the timing measurement conditions in the pci-x 1.0a specification . 2. minimum times are measured at the package pin (not the test point). maximum times are measured with the test point and load circuit. 3. setup time for point-to-point signals applies to req and gnt only. all other signals are bused. 4. for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 5. setup time applies only when the device is not driving the pin. devices cannot drive and receive signals at the same time. 6. maximum value is also limited by delay to the first transaction (time for hreset high to first configuration access, t pcrhfv ). the pci-x initialization pattern control signals after the rising edge of hreset must be negated no later than two clocks before the first frame and must be floated no later than one clock before frame is asserted. 7. a pci-x device is permitted to have the minimum values shown for t pckhov and t cyc only in pci-x mode. in conventional mode, the device must meet the requirements specified in pci 2.2 for the appropriate clock frequency. 8. device must meet this specification independent of how many outputs switch simultaneously. 9. the timing parameter t pcivkh is a minimum of 1.4 ns rather than the minimum of 1.2 ns in the pci-x 1.0a specification. 10.the timing parameter t pcrhfv is a minimum of 10 clocks rather than the minimum of 5 clocks in the pci-x 1.0a specification. 11.guaranteed by characterization. 12.guaranteed by design. table 46. rapidio 8/16 lp-lvds driver dc electrical characteristics at recommended operating conditions with ov dd of 3.3 v 5%. characteristic symbol min max unit notes differential output high voltage v ohd 247 454 mv 1, 2 differential output low voltage v old ?454 ?247 mv 1, 2 differential offset voltage v osd ?50mv1,3 output high common mode voltage v ohcm 1.125 1.375 v 1, 4 output low common mode voltage v olcm 1.125 1.375 v 1, 5 common mode offset voltage v oscm ?50mv1, 6 differential termination r term 90 220 w ? short circuit current (either output) |i ss |? 24ma7 table 45. pci-x ac timing specifications at 133 mhz (continued) parameter symbol min max unit notes
mpc8560 integrated processor hardware specifications, rev. 5 58 freescale semiconductor rapidio bridged short circuit current |i sb |? 12ma8 notes: 1. bridged 100- load. 2. see figure 41 (a). 3. differential offset voltage = |v ohd +v old |. see figure 41 (b). 4. v ohcm = (v oa + v ob )/2 when measuring v ohd . 5. v olcm = (v oa + v ob )/2 when measuring v old . 6. common mode offset v oscm = |v ohcm ? v olcm |. see figure 41 (c). 7. outputs shorted to v dd or gnd. 8. outputs shorted together. table 47. rapidio 8/16 lp-lvds receiver dc electrical characteristics characteristic symbol min max unit notes voltage at either input v i 02.4v? differential input high voltage v ihd 100 600 mv 1 differential input low voltage v ild ?600 ?100 mv 1 common mode input range (referenced to receiver ground) v icm 0.050 2.350 v 2 input differential resistance r in 90 110 w ? notes: 1. over the common mode range. 2. limited by v i . see figure 48 . table 46. rapidio 8/16 lp-lvds driver dc electrical characteristics (continued) at recommended operating conditions with ov dd of 3.3 v 5%. characteristic symbol min max unit notes
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 59 rapidio figure 41 shows the dc driver signal levels. figure 41. dc driver signal levels 13.2 rapidio ac electrical specifications this section contains the ac electrical specificati ons for a rapidio 8/16 lp-lvds device. the interface defined is a parallel differential low-power high-speed signal interface. note that the source of the transmit clock on the rapidio interface is dependent o n the settings of the lgpl[0:1] signals at reset. note that the default setting makes the core complex bus (ccb) clock the source of the transmit clock. see chapter 4 of the reference manual for more details on reset configuration settings. 13.3 rapidio concepts and definitions this section specifies signals using differential voltages. figure 42 shows how the signals are defined. the figure shows waveforms for either a transmitter output (td and td ) or a receiver input (rd and rd ). each signal swings between a volts and b volts where a > b. using these waveforms, the definitions are as follows: ? the transmitter output and receiver input signals td, td , rd, and rd each have a peak-to-peak swing of a-b volts. ? the differential output signal of the transmitter, v od , is defined as v td ? v td . ? the differential input signal of the receiver, v id , is defined as v rd ? v rd . ? the differential output signal of the transmitter or input signal of the receiver, ranges from a ? b volts to ? (a ? b) volts. v oa v ob r term 100 (no m) vv od = v oa ? v ob v os v ohcm v olcm v oscm = (v oa + v ob )/2 ?v + v od v v od = v oa ? v ob ?v ? v od ?v 0 1.375 v 1.125 v 454 mv 247 mv ?247 mv ?454 mv v old common-mode specifications (c) differential specifications (b) (a) note: v oa refers to voltage at output a; v ob refers to voltage at output b. v ohd
mpc8560 integrated processor hardware specifications, rev. 5 60 freescale semiconductor rapidio ? the peak differential signal of the transmitter output or receiver input, is a ? b volts. ? the peak-to-peak differential signal of th e transmitter output or receiver input, is 2 (a ? b) volts. figure 42. differential peak-to-peak voltage of transmitter or receiver to illustrate these definitions using numerical values, consider the case where a lvds transmitter has a common mode voltage of 1.2 v and each signal has a sw ing that goes between 1.4 and 1.0 v. using these values, the peak-to-peak voltage swing of the signals td, td , rd, and rd is 400 mv. the differential signal ranges between 400 and ?400 mv. the peak diff erential signal is 400 mv, and the peak-to-peak differential signal is 800 mv. a timing edge is the zero-crossing of a differential signal. each skew timing parameter on a parallel bus is synchronously measured on two signals relative to each other in the same cycle, such as data to data, data to clock, or clock to clock. a skew timing parameter may be relative to the edge of a signal or to the middle of two sequential edges. static skew represents the timing difference between signals that does not vary over time regardless of system activity or data pattern. path length di fferences are a primary source of static skew. dynamic skew represents the amount of timing differen ce between signals that is dependent on the activity of other signals and varies over time. crosstalk between signals is a source of dynamic skew. eye diagrams and compliance masks are a useful way to visualize and specify driver and receiver performance. this technique is used in several seri al bus specifications. an example compliance mask is shown in figure 43 . the key difference in the application of this technique for a parallel bus is that the data is source synchronous to its bus clock while serial data is referenced to its embedded clock. eye diagrams reveal the quality (cleanness, openness, goodness) of a driver output or receiver input. an advantage of using an eye diagram and a compliance mask is that it allows specifying the quality of a signal without requiring separate specifications for effects such as rise time, duty cycle distortion, data dependent dynamic skew, random dynamic skew, etc. this a llows the individual semiconductor manufacturer maximum flexibility to trade off various performance criteria while keeping the system performance constant. in using the eye pattern and compliance mask appr oach, the quality of the signal is specified by the compliance mask. the mask specifies the maximum permissible magnitude of the signal and the minimum permissible eye opening. the eye diagram for the signal under test is generated according to the specification. compliance is determined by whether the compliance mask can be positioned over the eye diagram such that the eye pattern falls entirely within the unshaded portion of the mask. serial specifications have cloc k encoded with the data, but the lp-lvds physical layer defined by rapidio is a source synchronous parallel port so additi onal specifications to include effects that are not found in serial links are required. specifications for the effect of bit to bit timing differences caused by static skew have been added and th e eye diagrams specified are measured relative to the associated clock in order to include clock to data effects. with the transmit output (or receiver input) eye diagram, the user can determine if the transmitter output (or receiver input) is compliant with an oscilloscope with the appropriate software. a v b v td or rd td or rd
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 61 rapidio figure 43. example compliance mask y = minimum data valid amplitude z = maximum amplitude 1 ui = 1 unit interval = 1/baud rate x1 = end of zero crossing region x2 = beginning of data valid window dv = data valid window = 1 ? 2 x2 the waveform of the signal under test must fall within the unshaded area of the mask to be compliant. different masks are used for the driver output and the receiver input allowing each to be separately specified. 13.3.1 rapidio driver ac timing specifications driver ac timing specifications are provided in table 48 , table 49 , and table 50 . a driver shall comply with the specifications for each data rate/frequency for which operation of the driver is specified. unless otherwise specified, these specifications are subject to the following conditions. ? the specifications apply over the supply voltage and ambient temperature ranges specified by the device vendor. ? the specifications apply for any combina tion of data patterns on the data signals. ? the output of a driver shall be connected to a 100 , 1%, differential (bridged) resistive load. ? clock specifications apply only to clock signals. ? data specifications apply only to data signals (frame, d[0:7]). table 48. rapidio driver ac timing specifications?500 mbps data rate characteristic symbol range unit notes min max differential output high voltage v ohd 200 540 mv 1 differential output low voltage v old ?540 ?200 mv 1 x2 z 0 y ?y ?z 1?x2 dv differential (v) time (ui) 01 x1 1?x1
mpc8560 integrated processor hardware specifications, rev. 5 62 freescale semiconductor rapidio duty cycle dc 48 52 % 2, 6 v od rise time, 20%?80% of peak-to-peak differential signal swing t fall 200 ? ps 3, 6 v od fall time, 20%?80% of peak-to-peak differential signal swing t rise 200 ? ps 6 data valid dv 1260 ? ps skew of any two data outputs t dpair ? 180 ps 4, 6 skew of single data outputs to associated clock t skew,pair ?180 180 ps 5, 6 notes: 1. see figure 44 . 2. requires 100 ppm long term frequency stability. 3. measured at v od = 0 v. 4. measured using the rapidio transmit mask shown in figure 44 . 5. see figure 49 . 6. guaranteed by design. table 49. rapidio driver ac timing specifications?750 mbps data rate characteristic symbol range unit notes min max differential output high voltage v ohd 200 540 mv 1 differential output low voltage v old ?540 ?200 mv 1 duty cycle dc 48 52 % 2, 6 v od rise time, 20%?80% of peak-to-peak differential signal swing t fall 133 ? ps 3, 6 v od fall time, 20%?80% of peak-to-peak differential signal swing t rise 133 ? ps 6 data valid dv 800 ? ps 6 skew of any two data outputs t dpair ? 133 ps 4, 6 skew of single data outputs to associated clock t skew,pair ?133 133 ps 5, 6 notes: 1. see figure 44 . 2. requires 100 ppm long term frequency stability. 3. measured at v od = 0 v. 4. measured using the rapidio transmit mask shown in figure 44 . 5. see figure 49 . 6. guaranteed by design. table 48. rapidio driver ac timing specifications?500 mbps data rate (continued) characteristic symbol range unit notes min max
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 63 rapidio the compliance of driver output signals td[0:15] and tframe with their minimum data valid window (dv) specification shall be determined by generating an eye pattern for each of the data signals and comparing the eye pattern of each data signal with the rapidio transmit mask shown in figure 44 . the value of x2 used to construct the mask shall be (1 ? dv min )/2. a signal is compliant with the data valid window specification if the transmit mask can be positioned on the signal?s eye pattern such that the eye pattern falls entirely within th e unshaded portion of the mask. figure 44. rapidio transmit mask table 50. rapidio driver ac timing specifications?1 gbps data rate characteristic symbol range unit notes min max differential output high voltage v ohd 200 540 mv 1 differential output low voltage v old ?540 ?200 mv 1 duty cycle dc 48 52 % 2, 6 v od rise time, 20%?80% of peak to peak differential signal swing t fall 100 ? ps 3, 6 v od fall time, 20%?80% of peak to peak differential signal swing t rise 100 ? ps 6 data valid dv 575 ? ps 6 skew of any two data outputs t dpair ? 100 ps 4, 6 skew of single data outputs to associated clock t skew,pair ?100 100 ps 5, 6 notes: 1. see figure 44 . 2. requires 100 ppm long term frequency stability. 3. measured at v od = 0 v. 4. measured using the rapidio transmit mask shown in figure 44 . 5. see figure 49 . 6. guaranteed by design. x2 v ohdmax 0 v ohdmin v oldmax v oldmin 1?x2 dv v od (mv) time (ui) 01
mpc8560 integrated processor hardware specifications, rev. 5 64 freescale semiconductor rapidio the eye pattern for a data signal is generated by making a large number of recordings of the signal and then overlaying the recordings. the number of recordi ngs used to generate the eye shall be large enough that further increasing the number of recordings used does not cause the resulting eye pattern to change from one that complies with the rapidio transmit mask to one that does not. each data signal in the interface shall be carrying random or pseudo-random data when the recordings are made. if pseudo-random data is used, the length of the ps eudo-random sequence (repeat length) shall be long enough that increasing the length of the sequence does not cause the resulting eye pattern to change from one that complies with the rapidio transmit mask to one that does not comply with the mask. the data carried by any given data signal in the interface may not be correlated with the data carried by any other data signal in the interface. the zero-crossings of the clock associated with a data signal shall be used as the timing reference for aligning the multiple recordings of the data signal when the recordings are overlaid. while the method used to make the recordings and overl ay them to form the eye pattern is not specified, the method used shall be demonstr ably equivalent to the following method. the signal under test is repeatedly recorded with a digital oscilloscope in infinite persistence mode. each recording is triggered by a zero-crossing of the clock associated with the data signal under test. roughly half of the recordings are triggered by positive-going clock zero-crossings and roughly half are triggered by negative-going clock zero-crossings. each recording is at least 1.9 ui in length (to ensure that at least one complete eye is formed) and begins 0.5 ui before the trigger point (0.5 ui before the associated clock zero-crossing). depending on the length of the individual recordings used to generate the eye pattern, one or more complete eyes will be formed. regardless of the number of eyes, the eye whose center is immediately to the right of the trigger point is the eye used for compliance testing. an example of an eye pattern generated using the a bove method with recordings 3 ui in length is shown in figure 45 . in this example, there is no skew between the signal under test and the associated clock used to trigger the recordings. if skew was present, the eye pattern would be shifted to the left or right relative to the oscilloscope trigger point. . figure 45. example driver output eye pattern 0 + ? v od 0.5 ui 1.0 ui 1.0 ui oscilloscope (recording) trigger point eye pattern eye used for compliance testing
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 65 rapidio 13.3.2 rapidio receiver ac timing specifications the rapidio receiver ac timing specifications are provided in table 51 . a receiver shall comply with the specifications for each data rate/frequency for which operation of the receiver is specified. unless otherwise specified, these specifications are subject to the following conditions. ? the specifications apply over the supply voltage and ambient temperature ranges specified by the device vendor. ? the specifications apply for any combina tion of data patterns on the data signals. ? the specifications apply over the receiver co mmon mode and differential input voltage ranges. ? clock specifications apply only to clock signals. ? data specifications apply only to data signals (frame, d[0:7]) table 51. rapidio receiver ac timing specifications?500 mbps data rate characteristic symbol range unit notes min max duty cycle of the clock input dc 47 53 % 1, 5 data valid dv 1080 ps 2 allowable static skew between any two data inputs within a 8-/9-bit group t dpair ? 380 ps 3 allowable static skew of data inputs to associated clock t skew,pair ?300 300 ps 4 notes: 1. measured at v id = 0 v. 2. measured using the rapidio receive mask shown in figure 46 . 3. see figure 49 . 4. see figure 48 and figure 49 . 5. guaranteed by design. table 52. rapidio receiver ac timing specifications?750 mbps data rate characteristic symbol range unit notes min max duty cycle of the clock input dc 47 53 % 1, 5 data valid dv 600 ? ps 2 allowable static skew between any two data inputs within a 8-/9-bit group t dpair ? 400 ps 3 allowable static skew of data inputs to associated clock t skew,pair ?267 267 ps 4 notes: 1. measured at v id = 0 v. 2. measured using the rapidio receive mask shown in figure 46 . 3. see figure 49 . 4. see figure 48 and figure 49 . 5. guaranteed by design.
mpc8560 integrated processor hardware specifications, rev. 5 66 freescale semiconductor rapidio the compliance of receiver input signals rd[0:15] and rframe with their mi nimum data valid window (dv) specification shall be determined by generating an eye pattern for each of the data signals and comparing the eye pattern of each data signal with the rapidio receive mask shown in figure 46 . the value of x2 used to construct the mask shall be (1 ? dv min )/2. the 100 mv minimum data valid and 600 mv maximum input voltage values are from the dc specification. a signal is compliant with the data valid window specification if and only if the receive mask can be positioned on the signal?s eye pattern such that the eye pattern falls entirely within the unshaded portion of the mask. figure 46. rapidio receive mask the eye pattern for a data signal is generated by making a large number of recordings of the signal and then overlaying the recordings. the number of recordi ngs used to generate the eye shall be large enough that further increasing the number of recordings used does not cause the resulting eye pattern to change from one that complies with the rapidio receive mask to one that does not. each data signal in the interface shall be carrying random or pseudo-random data when the recordings are made. if pseudo-random data is used, the length of the ps eudo-random sequence (repeat length) shall be long table 53. rapidio receiver ac timing specifications?1 gbps data rate characteristic symbol range unit notes min max duty cycle of the clock input dc 47 53 % 1, 5 data valid dv 425 ? ps 2 allowable static skew between any two data inputs within a 8-/9-bit group t dpair ?300ps3 allowable static skew of data inputs to associated clock t skew,pair ?200 200 ps 4 notes: 1. measured at v id = 0 v. 2. measured using the rapidio receive mask shown in figure 46 . 3. see figure 49 . 4. see figure 48 and figure 49 . 5. guaranteed by design. x2 600 0 100 ?100 ?600 1?x2 dv v id (mv) time (ui) 01
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 67 rapidio enough that increasing the length of the sequence does not cause the resulting eye pattern to change from one that complies with the rapidio receive mask to one that does not comply with the mask. the data carried by any given data signal in the interface may not be correlated with the data carried by any other data signal in the interface. the zero-crossings of the clock associated with a data signal shall be used as the timing reference for aligning the multiple recordings of the data signal when the recordings are overlaid. while the method used to make the recordings and overl ay them to form the eye pattern is not specified, the method used shall be demonstr ably equivalent to the following method. the signal under test is repeatedly recorded with a digital oscilloscope in infinite persistence mode. each recording is triggered by a zero-crossing of the clock associated with the data signal under test. roughly half of the recordings are triggered by positive-going clock zero-crossings and roughly half are triggered by negative-going clock zero-crossings. each recording is at least 1.9 ui in length (to ensure that at least one complete eye is formed) and begins 0.5 ui before the trigger point (0.5 ui before the associated clock zero-crossing). depending on the length of the individual recordings used to generate the eye pattern, one or more complete eyes will be formed. regardless of the number of eyes, the eye whose center is immediately to the right of the trigger point is the eye used for compliance testing. an example of an eye pattern generated using the a bove method with recordings 3 ui in length is shown in figure 47 . in this example, there is no skew between the signal under test and the associated clock used to trigger the recordings. if skew was present, the eye pattern would be shifted to the left or right relative to the oscilloscope trigger point. figure 47. example receiver input eye pattern 0 + ? v id 0.5 ui 1.0 ui 1.0 ui oscilloscope (recording) trigger point eye pattern eye used for compliance testing
mpc8560 integrated processor hardware specifications, rev. 5 68 freescale semiconductor rapidio figure 48 shows the definitions of the data to clock static skew parameter t skew,pair and the data valid window parameter dv. the data and frame bits are thos e that are associated with the clock. the figure applies for all zero-crossings of the clock. all of the signals are differential signals. v d represents v od for the transmitter and v id for the receiver. the center of the eye is defined as the midpoint of the region in which the magnitude of the signal voltage is greater than or equal to the minimum dv voltage. figure 48. data to clock skew figure 49 shows the definition of the data to data static skew parameter t dpair and how the skew parameters are applied. figure 49. static skew diagram v d clock x t skew,pair 1.0 ui nominal 0.5 ui 0.5 dv 0.5 dv eye opening dv v hdmim v hdmim v d = 0 v v d = 0 v v d clock x d[0:7]/d[8:15], frame clk0 (clk1) 1.0 ui nominal 0.5 ui t dpair t skew,pair center point for clock d[0:7]/d[8:15], frame center point of the data valid window of the latest allowed data bit for data grouped late with respect to clock center point of the data valid window of the earliest allowed data bit for data grouped late with respect to clock
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 69 package and pin listings 14 package and pin listings this section details package paramete rs, pin assignments, and dimensions. 14.1 package parameters for the mpc8560 fc-pbga the package parameters are as provided in the following list. the package type is 29 mm 29 mm, 783 flip chip plastic ball grid array (fc-pbga). die size 12.2 mm 9.5 mm package outline 29 mm 29 mm interconnects 783 pitch 1 mm minimum module height 3.07 mm maximum module height 3.75 mm solder balls 62 sn/36 pb/2 ag ball diameter (typical) 0.5 mm
mpc8560 integrated processor hardware specifications, rev. 5 70 freescale semiconductor package and pin listings 14.2 mechanical dimensions of the mpc8560 fc-pbga figure 50 the mechanical dimensions and bottom surface nomenclature of the mpc8560, 783 fc-pbga package. figure 50. mechanical dimensions and bottom surface nomenclature of the mpc8560 fc-pbga notes 1. all dimensions are in millimeters. 2. dimensions and tolerances per asme y14.5m-1994. 3. maximum solder ball diameter measured parallel to datum a.
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 71 package and pin listings 4. datum a, the seating plane, is defined by the spherical crowns of the solder balls. 5. capacitors may not be present on all devices. 6. caution must be taken not to short capacitors or exposed metal capacitor pads on package top. 7. the socket lid must always be oriented to a1. 14.3 pinout listings table 54 provides the pin-out listing for the device, 783 fc-pbga package. table 54. mpc8560 pinout listing signal package pin number pin type power supply notes pci/pci-x pci_ad[63:0] aa14, ab14, ac14, ad14, ae14, af14, ag14, ah14, v15, w15, y15, aa15, ab15, ac15, ad15, ag15, ah15, v16, w16, ab16, ac16, ad16, ae16, af16, v17, w17, y17, aa17, ab17, ae17, af17, af18, ah6, ad7, ae7, ah7, ab8, ac8, af8, ag8, ad9, ae9, af9, ag9, ah9, w10, y10, aa10, ae11, af11, ag11, ah11, v12, w12, y12, ab12, ad12, ae12, ag12, ah12, v13, y13, ab13, ac13 i/o ov dd 17 pci_c_be [7:0] ag13, ah13, v14, w14, ah8, ab10, ad11, ac12 i/o ov dd 17 pci_par aa11 i/o ov dd ? pci_par64 y14 i/o ov dd ? pci_frame ac10 i/o ov dd 2 pci_trdy ag10 i/o ov dd 2 pci_irdy ad10 i/o ov dd 2 pci_stop v11 i/o ov dd 2 pci_devsel ah10 i/o ov dd 2 pci_idsel aa9 i ov dd ? pci_req64 ae13 i/o ov dd 5, 10 pci_ack64 ad13 i/o ov dd 2 pci_perr w11 i/o ov dd 2 pci_serr y11 i/o ov dd 2, 4 pci_req0 af5 i/o ov dd ? pci_req [1:4] af3, ae4, ag4, ae5 i ov dd ? pci_gnt [0] ae6 i/o ov dd ? pci_gnt [1:4] ag5, ah5, af6, ag6 o ov dd 5, 9
mpc8560 integrated processor hardware specifications, rev. 5 72 freescale semiconductor package and pin listings ddr sdram memory interface mdq[0:63] m26, l27, l22, k24, m24, m23, k27, k26, k22, j28, f26, e27, j26, j23, h26, g26, c26, e25, c24, e23, d26, c25, a24, d23, b23, f22, j21, g21, g22, d22, h21, e21, n18, j18, d18, l17, m18, l18, c18, a18, k17, k16, c16, b16, g17, l16, a16, l15, g15, e15, c14, k13, c15, d15, e14, d14, d13, e13, d12, a11, f13, h13, a13, b12 i/o gv dd ? mecc[0:7] n20, m20, l19, e19, c21, a21, g19, a19 i/o gv dd ? mdm[0:8] l24, h28, f24, l21, e18, e16, g14, b13, m19 o gv dd ? mdqs[0:8] l26, j25, d25, a22, h18, f16, f14, c13, c20 i/o gv dd ? mba[0:1] b18, b19 o gv dd ? ma[0:14] n19, b21, f21, k21, m21, c23, a23, b24, h23, g24, k19, b25, d27, j14, j13 ogv dd ? mwe d17 o gv dd ? mras f17 o gv dd ? mcas j16 o gv dd ? mcs [0:3] h16, g16, j15, h15 o gv dd ? mcke[0:1] e26, e28 o gv dd 11 mck[0:5] j20, h25, a15, d20, f28, k14 o gv dd ? mck [0:5] f20, g27, b15, e20, f27, l14 o gv dd ? msync_in m28 i gv dd ? msync_out n28 o gv dd ? local bus controller interface la[27] u18 o ov dd 5, 9 la[28:31] t18, t19, t20, t21 o ov dd 7, 9 lad[0:31] ad26, ad27, ad28, ac26, ac27, ac28, aa22, aa23, aa26, y21, y22, y26, w20, w22, w26, v19, t22, r24, r23, r22, r21, r18, p26, p25, p20, p19, p18, n22, n23, n24, n25, n26 i/o ov dd ? lale v21 o ov dd 8, 9 lbctl v20 o ov dd 9 lcke u23 o ov dd ? lclk[0:2] u27, u28, v18 o ov dd ? lcs [0:4] y27, y28, w27, w28, r27 o ov dd 18 lcs5 /dma_dreq2 r28 i/o ov dd 1 table 54. mpc8560 pinout listing (continued) signal package pin number pin type power supply notes
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 73 package and pin listings lcs6 /dma_dack2 p27 o ov dd 1 lcs7 /dma_ddone2 p28 o ov dd 1 ldp[0:3] aa27, aa28, t26, p21 i/o ov dd lgpl0/lsda10 u19 o ov dd 5, 9 lgpl1/lsdwe u22 o ov dd 5, 9 lgpl2/loe /lsdras v28 o ov dd 8, 9 lgpl3/lsdcas v27 o ov dd 5, 9 lgpl4/lgta /lupwait/ lpbse v23 i/o ov dd 22 lgpl5 v22 o ov dd 5, 9 lsync_in t27 i ov dd ? lsync_out t28 o ov dd ? lwe [0:1]/lsddqm[0:1]/lbs [0:1] ab28, ab27 o ov dd 1, 5, 9 lwe [2:3]/lsddqm[2:3]/lbs [2:3] t23, p24 o ov dd 1, 5, 9 dma dma_dreq [0:1] h5, g4 i ov dd ? dma_dack [0:1] h6, g5 o ov dd ? dma_ddone [0:1] h7, g6 o ov dd ? programmable interrupt controller mcp ag17 i ov dd ? ude ag16 i ov dd ? irq[0:7] aa18, y18, ab18, ag24, aa21, y19, aa19, ag25 i ov dd ? irq8 ab20 i ov dd 9 irq9/dma_dreq3 y20 i ov dd 1 irq10/dma_dack3 af26 i/o ov dd 1 irq11/dma_ddone3 ah24 i/o ov dd 1 irq_out ab21 o ov dd 2, 4 ethernet management interface ec_mdc f1 o ov dd 5, 9 ec_mdio e1 i/o ov dd ? table 54. mpc8560 pinout listing (continued) signal package pin number pin type power supply notes
mpc8560 integrated processor hardware specifications, rev. 5 74 freescale semiconductor package and pin listings gigabit reference clock ec_gtx_clk125 e2 i lv dd ? three-speed ethernet controller (gigabit ethernet 1) tsec1_txd[7:4] a6, f7, d7, c7 o lv dd 5, 9 tsec1_txd[3:0] b7, a7, g8, e8 o lv dd 9, 19 tsec1_tx_en c8 o lv dd 11 tsec1_tx_er b8 o lv dd ? tsec1_tx_clk c6 i lv dd ? tsec1_gtx_clk b6 o lv dd 18 tsec1_crs c3 i lv dd ? tsec1_col g7 i lv dd ? tsec1_rxd[7:0] d4, b4, d3, d5, b5, a5, f6, e6 i lv dd ? tsec1_rx_dv d2 i lv dd ? tsec1_rx_er e5 i lv dd ? tsec1_rx_clk d6 i lv dd ? three-speed ethernet controller (gigabit ethernet 2) tsec2_txd[7:2] b10, a10, j10, k11,j11, h11 o lv dd 5, 9 tsec2_txd[1:0] g11, e11 o lv dd ? tsec2_tx_en b11 o lv dd 11 tsec2_tx_er d11 o lv dd ? tsec2_tx_clk d10 i lv dd ? tsec2_gtx_clk c10 o lv dd 18 tsec2_crs d9 i lv dd ? tsec2_col f8 i lv dd ? tsec2_rxd[7:0] f9, e9, c9, b9, a9, h9, g10, f10 i lv dd ? tsec2_rx_dv h8 i lv dd ? tsec2_rx_er a8 i lv dd ? tsec2_rx_clk e10 i lv dd ? rapidio interface rio_rclk y25 i ov dd ? rio_rclk y24 i ov dd ? table 54. mpc8560 pinout listing (continued) signal package pin number pin type power supply notes
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 75 package and pin listings rio_rd[0:7] t25, u25, v25, w25, aa25, ab25, ac25, ad25 i ov dd ? rio_rd [0:7] t24, u24, v24, w24, aa24, ab24, ac24, ad24 i ov dd ? rio_rframe ae27 i ov dd ? rio_rframe ae26 i ov dd ? rio_tclk ac20 o ov dd 11 rio_tclk ae21 o ov dd 11 rio_td[0:7] ae18, ac18, ad19, ae20, ad21, ae22, ac22, ad23 o ov dd ? rio_td [0:7] ad18, ae19, ac19, ad20, ac21, ad22, ae23, ac23 o ov dd ? rio_tframe ae24 o ov dd ? rio_tframe ae25 o ov dd ? rio_tx_clk_in af24 i ov dd ? rio_tx_clk_in af25 i ov dd ? i 2 c interface iic_sda ah22 i/o ov dd 4, 20 iic_scl ah23 i/o ov dd 4, 20 system control hreset ah16 i ov dd ? hreset_req ag20 o ov dd ? sreset af20 i ov dd ? ckstp_in m11 i ov dd ? ckstp_out g1 o ov dd 2, 4 debug trig_in n12 i ov dd ? trig_out/ready g2 o ov dd 6, 9, 19 msrcid[0:1] j9, g3 o ov dd 5, 6, 9 msrcid[2:4] f3, f5, f2 o ov dd 6 mdval f4 o ov dd 6 clock sysclk ah21 i ov dd ? rtc ab23 i ov dd ? clk_out af22 o ov dd 11 table 54. mpc8560 pinout listing (continued) signal package pin number pin type power supply notes
mpc8560 integrated processor hardware specifications, rev. 5 76 freescale semiconductor package and pin listings jtag tck af21 i ov dd ? tdi ag21 i ov dd 12 tdo af19 o ov dd 11 tms af23 i ov dd 12 trst ag23 i ov dd 12 dft lssd_mode ag19 i ov dd 21 l1_tstclk ab22 i ov dd 21 l2_tstclk ag22 i ov dd 21 test_sel ah20 i ov dd 3 thermal management therm0 ag2 i ? 14 therm1 ah3 i ? 14 power management asleep ag18 i/o 9, 19 power and ground signals av dd 1 ah19 power for e500 pll (1.2 v) av dd 1 ? av dd 2 ah18 power for ccb pll (1.2 v) av dd 2 ? av dd 3 ah17 power for cpm pll (1.2 v) av dd 3 ? gnd a12, a17, b3, b14, b20, b26, b27, c2, c4, c11,c17, c19, c22, c27, d8, e3, e12, e24, f11, f18, f23, g9, g12, g25, h4, h12, h14, h17, h20, h22, h27, j19, j24, k5, k9, k18, k23, k28, l6, l20, l25, m4, m12, m14, m16, m22, m27, n2, n13, n15, n17, p12, p14, p16, p23, r13, r15, r17, r20, r26, t3, t8, t10, t12, t14, t16, u6, u13, u15, u16, u17, u21, v7, v10, v26, w5, w18, w23, y8, y16, aa6, aa13, ab4, ab11, ab19, ac6, ac9, ad3, ad8, ad17, af2, af4, af10, af13, af15, af27, ag3, ag7, ag26 ?? ? gv dd a14, a20, a25, a26, a27, a28, b17, b22, b28, c12, c28, d16, d19, d21, d24, d28, e17, e22, f12, f15, f19, f25, g13, g18, g20, g23, g28, h19, h24, j12, j17, j22, j27, k15, k20, k25, l13, l23, l28, m25, n21 power for ddr dram i/o voltage (2.5 v) gv dd ? table 54. mpc8560 pinout listing (continued) signal package pin number pin type power supply notes
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 77 package and pin listings lv dd a4, c5, e7, h10 reference voltage; three-speed ethernet i/o (2.5 v, 3.3 v) lv dd ? mv ref n27 reference voltage signal; ddr mv ref ? no connects ah26, ah27, ah28, ag28, af28, ae28, ah1, ag1, ah2, b1, b2, a2, a3, ah25 ??16 ov dd d1, e4, h3, k4, k10, l7, m5, n3, p22, r19, r25, t2, t7, u5, u20, u26, v8, w4, w13, w19, w21, y7, y23, aa5, aa12, aa16, aa20, ab7, ab9, ab26, ac5, ac11, ac17, ad4, ae1, ae8, ae10, ae15, af7, af12, ag27, ah4 pci/pci-x, rapidio, 10/100 ethernet, and other standard (3.3 v) ov dd ? reserved c1, t11, u11, af1 ? ? 15 sensevdd l12 power for core (1.2 v) v dd 13 sensevss k12 ? ? 13 v dd m13, m15, m17, n14, n16, p13, p15, p17, r12, r14, r16, t13, t15, t17, u12, u14 power for core (1.2 v) v dd ? cpm pa[0:31] h1, h2, j1, j2, j3, j4, j5, j6, j7, j8, k8, k7, k6, k3, k2, k1, l1, l2, l3, l4, l5, l8, l9, l10, l11, m10, m9, m8, m7, m6, m3, m2 i/0 ov dd ? pb[4:31] m1, n1, n4, n5, n6, n7, n8, n9, n10, n11, p11, p10, p9, p8, p7, p6, p5, p4, p3, p2, p1, r1, r2, r3, r4, r5, r6, r7 i/0 ov dd ? pc[0:31] r8, r9, r10, r11, t9, t6, t5, t4, t1, u1, u2, u3, u4, u7, u8, u9, u10, v9, v6, v5, v4, v3, v2, v1, w1, w2, w3, w6, w7, w8, w9, y9 i/0 ov dd ? table 54. mpc8560 pinout listing (continued) signal package pin number pin type power supply notes
mpc8560 integrated processor hardware specifications, rev. 5 78 freescale semiconductor package and pin listings pd[4:31] y1, y2, y3, y4, y5, y6, aa8, aa7, aa4, aa3, aa2, aa1, ab1, ab2, ab3, ab5, ab6, ac7, ac4, ac3, ac2, ac1, ad1, ad2, ad5, ad6, ae3, ae2 i/0 ov dd ? notes: 1. all multiplexed signals are listed only once and do not re-occur. for example, lcs5 /dma_req2 is listed only once in the local bus controller interface section, and is not mentioned in the dma section even though the pin also functions as dma_req2 . 2. recommend a weak pull-up resistor (2?10 k ) be placed on this pin to ov dd . 3. this pin must always be pulled up to ov dd . 4. this pin is an open drain signal. 5. this pin is a reset configuration pin. it has a weak internal pull-up p-fet which is enabled only when the device is in the r eset state. this pull-up is designed such that it can be overpowered by an external 4.7-k pull-down resistor. if an external device connected to this pin might pull it down during reset, then a pull-up or active driver is needed if the signal is intended to b e high during reset. 6. treat these pins as no connects (nc) unless using debug address functionality. 7. the value of la[28:31] during reset sets the ccb clock to sysclk pll ratio. these pins require 4.7-k pull-up or pull-down resistors. see section 15.2, ?platform/system pll ratio .? 8. the value of lale and lgpl2 at reset set the e500 core clock to ccb clock pll ratio. these pins require 4.7-k pull-up or pull-down resistors. see the section 15.3, ?e500 core pll ratio .? 9. functionally, this pin is an output, but structurally it is an i/o because it either samples configuration input during reset or because it has other manufacturing test functions. this pin will therefore be described as an i/o for boundary scan. 10.this pin functionally requires a pull-up resistor, but during reset it is a configuration input that controls 32- vs. 64-bit pci operation. therefore, it must be actively driven low during reset by reset logic if the device is to be configured to be a 64-b it pci device. refer to the pci specification . 11.this output is actively driven during reset rather than being three-stated during reset. 12.these jtag pins have weak internal pull-up p-fets that are always enabled. 13.these pins are connected to the v dd /gnd planes internally and may be used by the core power supply to improve tracking and regulation. 14.internal thermally sensitive resistor. 15.no connections should be made to these pins. 16.these pins are not connected for any functional use. 17.pci specifications recommend that a weak pull-up resistor (2?10 k ) be placed on the higher order pins to ov dd when using 64-bit buffer mode (pins pci_ad[63:32] and pci_c_be[7:4]). 18.note that these signals are por configurations for rev. 1.x and notes 5 and 9 apply to these signals in rev. 1.x but not in later revisions. 19 if this pin is connected to a device that pulls down during reset, an external pull-up is required to drive this pin to a lo gic ?1 state during reset. 20.recommend a pull-up resistor (~1 k ) b placed on this pin to ov dd . 21.these are test signals for factory use only and must be pulled up (100 - 1 k ) to ovdd for normal machine operation. 22.if this signal is used as both an input and an output, a weak pull-up (~10 k ) is required on this pin. table 54. mpc8560 pinout listing (continued) signal package pin number pin type power supply notes
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 79 clocking 15 clocking this section describes the pll configuration of the devi ce. note that the platform clock is identical to the ccb clock. 15.1 clock ranges table 55 provides the clocking specifications for the processor core and table 56 provides the clocking specifications for the memory bus. table 55. processor core clocking specifications characteristic maximum processor core frequency unit notes 667 mhz 833 mhz 1 ghz min max min max min max e500 core processor frequency 400 667 400 833 400 1000 mhz 1, 2, 3 notes : 1. caution: the ccb to sysclk ratio and e500 core to ccb ratio settings must be chosen such that the resulting sysclk frequency, e500 (core) frequency, and ccb frequency do not exceed their respective maximum or minimum operating frequencies. refer to section 15.2, ?platform/system pll ratio ,? and section 15.3, ?e500 core pll ratio ,? for ratio settings. 2.)the minimum e500 core frequency is based on the minimum platform frequency of 200 mhz. 3.)the 1.0 ghz core frequency is based on a 1.3 v vdd supply voltage. table 56. memory bus clocking specifications characteristic maximum processor core frequency unit notes 667 mhz 833 mhz 1 ghz min max min max min max memory bus frequency 100 166 100 166 100 166 mhz 1, 2, 3 notes: 1. caution: the ccb to sysclk ratio and e500 core to ccb ratio settings must be chosen such that the resulting sysclk frequency, e500 (core) frequency, and ccb frequency do not exceed their respective maximum or minimum operating frequencies. refer to section 15.2, ?platform/system pll ratio ,? and section 15.3, ?e500 core pll ratio ,? for ratio settings. 2. the memory bus speed is half of the ddr data rate, hence, half of the platform clock frequency. 3.)the 1.0 ghz core frequency is based on a 1.3 v vdd supply voltage.
mpc8560 integrated processor hardware specifications, rev. 5 80 freescale semiconductor clocking 15.2 platform/system pll ratio the platform clock is the clock that drives the l2 cache, the ddr sdram data rate, and the e500 core complex bus (ccb), and is also called the ccb clock. the values are determined by the binary value on la[28:31] at power up, as shown in table 57 . there is no default for this pll ratio; these signals must be pulled to the desired values. 15.3 e500 core pll ratio table 58 describes the clock ratio between the e500 core complex bus (ccb) and the e500 core clock. this ratio is determined by the binary value of lale and lgpl2 at power up, as shown in table 58 . table 57. ccb clock ratio binary value of la[28:31] signals ratio description 0000 16:1 ratio ccb clock: sysclk (pci bus) 0001 reserved 0010 2:1 ratio ccb clock: sysclk (pci bus) 0011 3:1 ratio ccb clock: sysclk (pci bus) 0100 4:1 ratio ccb clock: sysclk (pci bus) 0101 5:1 ratio ccb clock: sysclk (pci bus) 0110 6:1 ratio ccb clock: sysclk (pci bus) 0111 reserved 1000 8:1 ratio ccb clock: sysclk (pci bus) 1001 9:1 ratio ccb clock: sysclk (pci bus) 1010 10:1 ratio ccb clock: sysclk (pci bus) 1011 reserved 1100 12:1 ratio ccb clock: sysclk (pci bus) 1101 reserved 1110 reserved 1111 reserved table 58. e500 core to ccb ratio binary value of lale, lgpl2 signals ratio description 00 2:1 e500 core:ccb 01 5:2 e500 core:ccb 10 3:1 e500 core:ccb 11 7:2 e500 core:ccb
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 81 thermal 15.4 frequency options table 59 shows the expected frequency values for the platform frequency when using a ccb to sysclk ratio in comparison to the memory bus speed. 16 thermal this section describes the thermal specifications of the device. 16.1 thermal characteristics table 60 provides the package thermal characteristics for the mpc8560. table 59. frequency options with respect to memory bus speeds ccb to sysclk ratio sysclk (mhz) 16.67 25 33.33 41.63 66.67 83 100 111 133.33 platform/ccb frequency (mhz) 2 200 222 267 3 200 250 300 333 4 267 333 5 208 333 6 200 250 8 200 267 333 9 225 300 10 250 333 12 200 300 16 267 table 60. package thermal characteristics characteristic symbol value unit notes junction-to-ambient natural convection on four layer board (2s2p) r jma 16 c/w 1, 2 junction-to-ambient (@100 ft/min or 0.5 m/s) on four layer board (2s2p) r jma 14 c/w 1, 2 junction-to-ambient (@200 ft/min or 1 m/s) on four layer board (2s2p) r jma 12 ?c/w c/w 1, 2 junction-to-board thermal r jb 7.5 ?c/w c/w 3
mpc8560 integrated processor hardware specifications, rev. 5 82 freescale semiconductor thermal 16.2 thermal management information this section provides thermal management information for the flip chip plastic ball grid array (fc-pbga) package for air-cooled applications. proper ther mal control design is pr imarily dependent on the system-level design?the heat sink, airflow, and th ermal interface material. the recommended attachment method to the heat sink is illustrated in figure 51 . the heat sink should be attached to the printed-circuit board with the spring force centered over the die. this spring force should not exceed 10 pounds force. figure 51. package exploded cross-sectional view with several heat sink options the system board designer can choose between several types of heat sinks to place on the device. there are several commercially-available heat sinks from the following vendors: aavid thermalloy 603-224-9988 80 commercial st. concord, nh 03301 internet: www.aavidthermalloy.com junction-to-case thermal r jc 0.8 ?c/w c/w 4 notes 1. junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance 2. per jedec jesd51-6 with the board horizontal. 3. thermal resistance between the die and the printed-circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 4. thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1). cold plate temperature is used for case temperature; measured value includes the thermal resistance of the interface layer. table 60. package thermal characteristics (continued) characteristic symbol value unit notes thermal interface material heat sink fc-pbga package heat sink clip printed-circuit board die lid adhesive or
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 83 thermal alpha novatech 408-749-7601 473 sapena ct. #15 santa clara, ca 95054 internet: www.alphanovatech.com international electronic research corporation (ierc) 818-842-7277 413 north moss st. burbank, ca 91502 internet: www.ctscorp.com millennium electronics (mei) 408-436-8770 loroco sites 671 east brokaw road san jose, ca 95112 internet: www.mei-millennium.com tyco electronics 800-522-6752 chip coolers? p.o. box 3668 harrisburg, pa 17105-3668 internet: www.chipcoolers.com wakefield engineering 603-635-5102 33 bridge st. pelham, nh 03076 internet: www.wakefield.com ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal performance at a given air velocity , spatial volume, mass, attachment method, assembly, and cost. several heat sinks offered by aavid thermalloy, alpha novatech, ierc, chip coolers, millennium electronics, and wakefield engineering offer different heat sink-to-ambient thermal resistances, that will allow the device to function in various environments. 16.2.1 recommended thermal model for system thermal modeling, the device thermal model is shown in figure 50 . five cuboids are used to represent this device. to simplify the model, the sold er balls and substrate are modeled as a single block 29x29x1.47 mm with the conductivity adjusted accordingly. for modeling, the planar dimensions of the die are rounded to the nearest mm, so the die is modeled as 10x12 mm at a thickness of 0.76 mm. the bump/underfill layer is modeled as a collapsed resi stance between the die and substrate assuming a conductivity of 0.6 in-plane and 1.9 w/m?k in the thickness dimension of 0.76 mm. the lid attach adhesive is also modeled as a collapsed resi stance with dimensions of 10x12x0.050 mm and the conductivity of 1 w/m?k. the nickel plated copper lid is modeled as 12x14x1 mm. note that the die and lid are not centered on the substrate; there is a 1.5 mm offset documented in the case outline drawing in figure 50 .
mpc8560 integrated processor hardware specifications, rev. 5 84 freescale semiconductor thermal figure 52. mpc8560 thermal model 16.2.2 internal package conduction resistance for the packaging technology, shown in table 60 , the intrinsic internal conduction thermal resistance paths are as follows: ? the die junction-to-case thermal resistance ? the die junction-to-board thermal resistance die lid substrate and solder balls heat source substrate side view of model (not to scale) top view of model (not to scale) x y z conductivity value unit lid (12 14 1 mm) k x 360 w/(m k) k y 360 k z 360 lid adhesive?collapsed resistance (10 12 0.050 mm) k x 1 k y 1 k z 1 die (10 12 0.76 mm) bump/underfill?collapsed resistance (10 12 0.070 mm) k x 0.6 k y 0.6 k z 1.9 substrate and solder balls (29 29 1.47 mm) k x 10.2 k y 10.2 k z 1.6 adhesive bump/underfill
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 85 thermal figure 53 depicts the primary heat transfer path for a pa ckage with an attached heat sink mounted to a printed-circuit board. figure 53. package with heat sink mounted to a printed-circuit board the heat sink removes most of the heat from the device. heat generated on the active side of the chip is conducted through the silicon and through the lid, then through the heat sink attach material (or thermal interface material), and finally to the heat sink. th e junction-to-case thermal resistance is low enough that the heat sink attach material and heat sink thermal resistance are the dominant terms. 16.2.3 thermal interface materials a thermal interface material is required at the package-to-heat sink interface to minimize the thermal contact resistance. for those applications where the heat sink is attached by spring clip mechanism, figure 54 shows the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/oil, floroether oil), a bare joint, and a join t with thermal grease as a function of contact pressure. as shown, the performance of these thermal interface materials improves with increasing contact pressure. the use of thermal grease significantly reduces the interface thermal resistance. the bare joint results in a thermal resistance approximately six times greater than the thermal grease joint. heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see figure 51 ). therefore, the synthetic grease offers the best thermal performance, especially at the low interface pressure. when removing the heat sink for re-work, it is preferable to slide the heat sink off slowly until the thermal interface material loses its grip. if the support fixture around the package prevents sliding off the heat sink, the heat sink should be slowly rem oved. heating the heat sink to 40-50 ? c with an air gun can soften the interface material and make the removal easier. the use of an adhesive for heat sink attach is not recommended. external resistance external resistance internal resistance radiation convection radiation convection heat sink printed-circuit board thermal interface material package/leads die junction die/package (note the internal versus external package resistance)
mpc8560 integrated processor hardware specifications, rev. 5 86 freescale semiconductor thermal figure 54. thermal performance of select thermal interface materials the system board designer can choose between severa l types of thermal interface. there are several commercially-available thermal inte rfaces provided by the following vendors: chomerics, inc. 781-935-4850 77 dragon ct. woburn, ma 01888-4014 internet: www.chomerics.com dow-corning corporation 800-248-2481 dow-corning electronic materials 2200 w. salzburg rd. midland, mi 48686-0997 internet: www.dowcorning.com shin-etsu microsi, inc. 888-642-7674 10028 s. 51st st. phoenix, az 85044 internet: www.microsi.com the bergquist company 800-347-4572 18930 west 78 th st. chanhassen, mn 55317 internet: www.bergquistcompany.com 0 0.5 1 1.5 2 0 1020304050607080 silicone sheet (0.006 in.) bare joint floroether oil sheet (0.007 in.) graphite/oil sheet (0.005 in.) synthetic grease contact pressure (psi) specific thermal resistance (k-in. 2 /w)
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 87 thermal thermagon inc. 888-246-9050 4707 detroit ave. cleveland, oh 44102 internet: www.thermagon.com 16.2.4 heat sink selection examples the following section provides a heat sink selection ex ample using one of the commercially available heat sinks. 16.2.4.1 case 1 for preliminary heat sink sizing, the die-junction temperature can be expressed as follows: t j = t i + t r + ( jc + int + sa ) p d where t j is the die-junction temperature t i is the inlet cabinet ambient temperature t r is the air temperature rise within the computer cabinet jc is the junction-to-case thermal resistance int is the adhesive or interface material thermal resistance sa is the heat sink base-to-ambient thermal resistance p d is the power dissipated by the device during operation the die-junction temperatures (t j ) should be maintained within the range specified in table 2 . the temperature of air cooling the component gr eatly depends on the ambient inlet air temperature and the air temperature rise within the electronic cabinet. an electronic cabinet inlet-air temperature (t a ) may range from 30 to 40 c. the air temperature rise within a cabinet (t r ) may be in the range of 5 to 10 c. the thermal resistance of some thermal interface material ( int ) may be about 1 c/w. assuming a t i of 30 c, a t r of 5 c, a fc-pbga package jc = 0.8, and a power consumption (p d ) of 7.0 w, the following expression for t j is obtained: die-junction temperature: t j = 30 c + 5 c + (0.8 c/w + 1.0 c/w + sa ) 7.0 w the heat sink-to-ambient thermal resistance ( sa ) versus airflow velocity for a thermalloy heat sink #2328b is shown in figure 55 . assuming an air velocity of 2 m/s, we have an effective sa+ of about 3.3 c/w, thus t j = 30 c + 5 c + (0.8 c/w +1.0 c/w + 3.3 c/w) 7.0 w, resulting in a die-junction temperature of approximately 71 c which is well within the maximum operating temperature of the component.
mpc8560 integrated processor hardware specifications, rev. 5 88 freescale semiconductor thermal figure 55. thermalloy #2328b heat sink-to-ambient thermal resistance versus airflow velocity 16.2.4.2 case 2 every system application has different conditions that the thermal management solution must solve. as an alternate example, assume that the air reaching the component is 85 c with an approach velocity of 1 m/sec. for a maximum junction temperature of 105 c at 7 w, the total thermal resistance of junction to case thermal resistance plus thermal interface material plus heat sink thermal resistance must be less than 2.8 c/w. the value of the junction to case thermal resistance in table 60 includes the thermal interface resistance of a thin layer of thermal grease as documented in footnote 4 of the table. assuming that the heat sink is flat enough to allow a thin layer of grease or phase change material, then the heat sink must be less than 2 c/w. millennium electronics (mei) has tooled a heat sink mtherm-1051 for this requirement assuming a compact pci environment at 1 m/sec and a heat sink height of 12 mm. the mei solution is illustrated in figure 56 and figure 57 . this design has several significant advantages: ? the heat sink is clipped to a plastic frame attached to the application board with screws or plastic inserts at the corners away from the primary signal routing areas. ? the heat sink clip is designed to apply the for ce holding the heat sink in place directly above the die at a maximum force of less than 10 lbs. ? for applications with significant vibration require ments, silicone damping material can be applied between the heat sink and plastic frame. 1 3 5 7 8 00.511.522.533.5 thermalloy #2328b pin-fin heat sink approach air velocity (m/s) heat sink thermal resistance ( c/w) (25 28 15 mm) 2 4 6
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 89 thermal the spring mounting should be designed to apply the fo rce only directly above the die. by localizing the force, rocking of the heat sink is minimized. one s uggested mounting method attaches a plastic fence to the board to provide the structure on which the heat sink spring clips. the plastic fence also provides the opportunity to minimize the holes in the printed-circuit board and to locate them at the corners of the package. figure 56 and figure 57 provide exploded views of the plastic fence, heat sink, and spring clip. figure 56. exploded views (1) of a heat sink attachment using a plastic force
mpc8560 integrated processor hardware specifications, rev. 5 90 freescale semiconductor thermal figure 57. exploded views (2) of a heat sink attachment using a plastic fence the die junction-to-ambient and the heat sink-to-amb ient thermal resistances are common figure-of-merits used for comparing the thermal performance of various microelectronic packaging technologies, one should exercise caution when only using this metric in determining thermal management because no single parameter can adequately descri be three-dimensional heat flow . the final die-junction operating temperature is not only a function of the component-level thermal resistance, but the system level design and its operating conditions. in addition to the component ?s power consumption, a number of factors affect the final operating die-junction temperature: airflo w, board population (local heat flux of adjacent components), system air temperature rise, altitude, etc. due to the complexity and the many variations of system-level boundary conditions for today?s microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation convection and conduction) may vary widely. for these reasons, we recommend using conjugate heat transfer models for the boards, as well as, system-level designs.
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 91 system design information 17 system design information this section provides electrical and thermal design recommendations for successful application of the device. 17.1 system clocking the mpc8560 includes three plls. 1. the platform pll generates the platform clock from the externally supplied sysclk input. the frequency ratio between the platform and sysclk is selected using the platform pll ratio configuration bits as described in section 15.2, ?platform/system pll ratio.? 2. the e500 core pll generates the core clock as a slave to the platform clock. the frequency ratio between the e500 core clock and the platform clock is selected using the e500 pll ratio configuration bits as described in section 15.3, ?e500 core pll ratio.? 3. the cpm pll is slaved to the platform clock and is used to generate clocks used internally by the cpm block. the ratio between the cpm pll and th e platform clock is fixed and not under user control. 17.2 pll power supply filtering each of the plls listed above is provided with power through independent power supply pins (av dd 1, av dd 2, and av dd 3, respectively). the av dd level should always be equivalent to v dd , and preferably these voltages will be derived directly from v dd through a low frequency filter scheme such as the following. there are a number of ways to reliably provide power to the plls, but the recommended solution is to provide three independent filter circuits as illustrated in figure 58 , one to each of the three av dd pins. by providing independent filters to each pll the opportunity to cause noise injection from one pll to the other is reduced. this circuit is intended to filter noise in the p lls resonant frequency range from a 500 khz to 10 mhz range. it should be built with surface mount capacitor s with minimum effective series inductance (esl). consistent with the recommendations of dr. howard johnson in high speed digital design: a handbook of black magic (prentice hall, 1993), multiple small capacito rs of equal value are recommended over a single large value capacitor. each circuit should be placed as cl ose as possible to the specific av dd pin being supplied to minimize noise coupled from nearby circuits. it should be possible to route directly from the capacitors to the av dd pin, which is on the periphery of the 783 fc-pbga footprint, without the inductance of vias.
mpc8560 integrated processor hardware specifications, rev. 5 92 freescale semiconductor system design information figure 58 shows the pll power supply filter circuit. figure 58. pll power supply filter circuit 17.3 decoupling recommendations due to large address and data buses, and high operati ng frequencies, the device can generate transient power surges and high frequency noise in its power suppl y, especially while driving large capacitive loads. this noise must be prevented from reaching other components in the mpc8560 system, and the device itself requires a clean, tightly regulated source of power. therefore, it is recommended that the system designer place at least one decoupling capacitor at each v dd , ov dd , gv dd , and lv dd pins of the device. these decoupling capacitors should receive their power from separate v dd , ov dd , gv dd , lv dd , and gnd power planes in the pcb, utilizing short traces to minimize inductance. capacitors may be placed directly under the device using a standard escape pattern. others may surround the part. these capacitors should have a value of 0.01 or 0.1 f. only ceramic smt (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes. in addition, it is recommended that there be several bulk storage capacitors distributed around the pcb, feeding the v dd , ov dd , gv dd , and lv dd planes, to enable quick recharging of the smaller chip capacitors. these bulk capacitors should have a low esr (equivalent series resistance) rating to ensure the quick response time necessary. they should also be connected to the power and ground planes through two vias to minimize inductance. suggested bulk capacitors?100?330 f (avx tps tantalum or sanyo oscon). 17.4 connection recommendations to ensure reliable operation, it is highly recommende d to connect unused inputs to an appropriate signal level. unused active low inputs should be tied to ov dd , gv dd , or lv dd as required. unused active high inputs should be connected to gnd. all nc (no-connect) signals must remain unconnected. power and ground connections must be made to all external v dd , gv dd , lv dd , ov dd , and gnd pins of the device. 17.5 output buffer dc impedance the mpc8560 drivers are characterized over process, voltage, and temperature. there are two driver types: a push-pull single-ended driver (open drain for i 2 c) for all buses except rapidio, and a current-steering differential driver for the rapidio port. to measure z 0 for the single-ended drivers, an external resistor is connected from the chip pad to ov dd or gnd. then, the value of each resistor is varied until the pad voltage is ov dd /2 (see figure 59 ). the output impedance is the average of two components, the resistances of the pull-up and pull-down devices. v dd av dd (or l2av dd ) 2.2 f 2.2 f gnd low esl surface mount capacitors 10
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 93 system design information when data is held high, sw1 is closed (sw2 is open) and r p is trimmed until the voltage at the pad equals ov dd /2. r p then becomes the resistance of the pull-up devices. r p and r n are designed to be close to each other in value. then, z 0 = (r p + r n )/2. figure 59. driver impedance measurement the output impedance of the rapidio port drivers targets 200- differential resistance. the value of this resistance and the strength of the driver?s current source can be found by making two measurements. first, the output voltage is measured while driving logic 1 w ithout an external differential termination resistor. the measured voltage is v 1 = r source i source . second, the output voltage is measured while driving logic 1 with an external precision differential termination resistor of value r term . the measured voltage is v 2 = 1/(1/r 1 +1/r 2 )) i source . solving for the output impedance gives r source = r term (v 1 /v 2 ?1). the drive current is then i source =v 1 /r source . table 61 summarizes the signal impedance targets. the driver impedance are targeted at minimum v dd , nominal ov dd , 105 c. table 61. impedance characteristics impedance local bus, ethernet, duart, control, configuration, power management pci/pci-x ddr dram rapidio symbol unit r n 43 target 25 target 20 target na z 0 w r p 43 target 25 target 20 target na z 0 w differential na na na 200 target z diff w note: nominal supply voltages. see ta ble 1 , t j = 105 c. ov dd ognd r p r n pad data sw1 sw2
mpc8560 integrated processor hardware specifications, rev. 5 94 freescale semiconductor system design information 17.6 configuration pin muxing the mpc8560 provides the user with power-on configuration options which can be set through the use of external pull-up or pull-down resistors of 4.7 k on certain output pins (see cu stomer visible configuration pins). these pins are generally used as output only pins in normal operation. while hreset is asserted however, these pins are treated as inputs. the value presented on these pins while hreset is asserted, is latched when hreset deasserts, at which time the input receiver is disabled and the i/o circuit takes on its normal function. most of these sampled configuration pins are equipped with an on-chip gated resi stor of approximately 20 k . this value should permit the 4.7-k resistor to pull the configuration pin to a valid logic low level. the pull-up resistor is enabled only during hreset (and for platform/system clocks after hreset deassertion to ensure capture of the reset value). when the input receiver is disabled the pull-up is also, thus allowi ng functional operation of the pin as an output with minimal signal quality or delay disruption. the default va lue for all configuration bits treated this way has been encoded such that a high voltage level puts the de vice into the default state and external resistors are needed only when non-default settings are required by the user. careful board layout with stubless connections to th ese pull-down resistors coupled with the large value of the pull-down resistor should minimize the disruption of signal quality or speed for output pins thus configured. the platform pll ratio and e500 pll ratio configura tion pins are not equipped with these default pull-up devices. 17.7 pull-up resistor requirements the mpc8560 requires high resistance pull-up resistors (10 k is recommended) on open drain type pins including epic interrupt pins. i 2 c open drain type pins should be pulled up with ~1 k resistors. correct operation of the jtag interface requires configuration of a group of system control pins as demonstrated in figure 61 . care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions as most have asynchronous behavior and spurious assertion will give unpredictable results. tsec1_txd[3:0] must not be pulled low during reset. some phy chips have internal pulldowns that could cause this to happen. if such phy chips are used , then a pullup must be placed on these signals strong enough to restore these signals to a logical 1 during reset. three test pins also require pull-up resistors (100 - 1 k ). these pins are l1_tstclk, l2_tstclk, and lssd_mode . these signals are for factory use only and must be pulled up to ovdd for normal machine operation. see the pci 2.2 specification for all pull-ups required for pci.
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 95 system design information 17.8 jtag configuration signals boundary-scan testing is enabled through the jtag interface signals. the trst signal is optional in the ieee 1149.1 specification, but is provided on all pro cessors that implement th e power architecture. the device requires trst to be asserted during reset conditions to ensure the jtag boundary logic does not interfere with normal chip operation. while it is possible to force the tap controller to the reset state using only the tck and tms signals, generally systems will assert trst during the power-on reset flow. simply tying trst to hreset is not practical because the jtag interface is also used for accessing the common on-chip processor (cop) function. the cop function of these processors allow a remote computer system (typically, a pc with dedicated hardware and debugging software) to access and control the internal operations of the processor. the cop interface connects primarily through the jtag port of the processor, with some additional status monitoring signals. the cop port requires the ability to independently assert hreset or trst in order to fully control the processor. if the target system ha s independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or push-button switches, then the cop reset signals must be merged into these signals with logic. the arrangement shown in figure 60 allows the cop port to independently assert hreset or trst , while ensuring that the target can drive hreset as well. the cop interface has a standard header, shown in figure 60 , for connection to the target system, and is based on the 0.025" square-post, 0.100" centered header assembly (often called a berg header). the connector typically has pin 14 removed as a connector key. the cop header adds many benefits such as breakpoints, watchpoints, register and memory examination/modification, and othe r standard debugger features. an inexpensive option can be to leave the cop header unpopulated until needed. there is no standardized way to number the cop head er; consequently, many diff erent pin numbers have been observed from emulator vendors. some are numbe red top-to-bottom then left-to-right, while others use left-to-right then top-to-bottom, while still othe rs number the pins counter clockwise from pin 1 (as with an ic). regardless of the numbering, the signal placement recommended in figure 60 is common to all known emulators.
mpc8560 integrated processor hardware specifications, rev. 5 96 freescale semiconductor system design information figure 60. cop connector physical pinout 17.8.1 termination of unused signals if the jtag interface and cop header will not be used, freescale recommends the following connections: ?trst should be tied to hreset through a 0 k isolation resistor so that it is asserted when the system reset signal (hreset ) is asserted, ensuring that the jtag scan chain is initialized during the power-on reset flow. freescale recommends that the cop header be designed into the system as shown in figure 61 . if this is not possible, the isolation resistor will allow future access to trst in case a jtag interface may need to be wired onto the system in future debug situations. ? tie tck to ov dd through a 10 k resistor. this will prevent tck from changing state and reading incorrect data into the device. ? no connection is required for tdi, tms, or tdo. 3 13 9 5 1 6 10 15 11 7 16 12 8 4 key no pin 1 2 cop_tdo cop_tdi nc nc cop_trst cop_vdd_sense cop_chkstp_in nc nc gnd cop_tck cop_tms cop_sreset cop_hreset cop_chkstp_out
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 97 system design information figure 61. jtag interface connection hreset from target board sources cop_hreset 13 cop_sreset sreset nc 11 cop_vdd_sense 2 6 5 15 10 10 k 10 k cop_chkstp_in ckstp_in 8 cop_tms cop_tdo cop_tdi cop_tck tms tdo tdi 9 1 3 4 cop_trst 7 16 2 10 12 (if any) cop header 14 3 notes: 3. the key location (pin 14) is not physically present on the cop header. 10 k trst 1 10 k 10 k 10 k ckstp_out cop_chkstp_out 3 13 9 5 1 6 10 15 11 7 16 12 8 4 key no pin cop connector physical pinout 1 2 nc sreset 2. populate this with a 10 resistor for short-circuit/current-limiting protection. nc ov dd 10 k 10 k hreset 1 in order to fully control the processor as shown here. 4. although pin 12 is defined as a no-connect, some debug tools may use pin 12 as an additional gnd pin for 1. the cop port and target board should be able to independently assert hreset and trst to the processor improved signal integrity. tck 4 5 5. this switch is included as a precaution for bsdl testing. the switch should be open during bsdl testing to avoid accidentally asserting the trst line. if bsdl testing is not being performed, this switch should be closed or removed. 10 k 6 6. asserting sreset causes a machine check interrupt to the e500 core.
mpc8560 integrated processor hardware specifications, rev. 5 98 freescale semiconductor device nomenclature 18 device nomenclature ordering information for the parts fully covered by this specification document is provided in section 18.1, ?part numbers fully addressed by this document .? 18.1 part numbers fully addressed by this document table 62 provides the freescale part numbering nomenclat ure for the mpc8560. note that the individual part numbers correspond to a maximum processor core frequency. for available frequencies, contact your local freescale sales office. in addition to the pr ocessor frequency, the part numbering scheme also includes an application modifier which may specify special application conditions. each part number also contains a revision code which refers to the die mask revision number. table 62. part numbering nomenclature mpc nnnn t pp ff(f) c r product code part identifier temperature range 1 package 2 processor frequency 3, 4 platform frequency revision level mpc 8560 blank = 0 to 105 c c= -40 to 105 c px = fc-pbga vt = fc-pbga (pb-free) 833 = 833 mhz 667 = 667 mhz l = 333 mhz j= 266 mhz b = rev. 2.0 (svr = 0x80700020) c = rev. 2.1 (svr = 0x80700021) d = rev. 2.1.1 (svr = 0x80700021) mpc 8560 blank = 0 to 105 c c = ?40 to 105 c px = fc-pbga vt = fc-pbga (pb-free) aq = 1.0 ghz f = 333 mhz b = rev. 2.0 (svr = 0x80700020) c = rev. 2.1 (svr = 0x80700021) d = rev. 2.1.1 (svr = 0x80700021) notes: 1. for temperature range=c, processor frequency is limited to 667 mhz. 2. see section 14, ?package and pin listings ,? for more information on available package types. 3. processor core frequencies supported by parts addressed by this specification only. not all parts described in this specifica tion support all core frequencies. the core must be clocked at a minimum frequency of 400 mhz. a device must not be used beyond the core frequency or platform frequency indicated on the device. 4. designers should use the maximum power value corresponding to the core and platform frequency grades indicated on the device. a lower maximum power value should not be assumed for design purposes even when running at a lower frequency.
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 99 document revision history 18.2 part marking parts are marked as the example shown in figure 62 . figure 62. part marking for fc-pbga device 19 document revision history table 63 provides a revision history for this hardware specification. table 63. document revision history rev. number date substantive change(s) 5 05/2010 in tab le 6 2 , ?part numbering nomenclature,? added information for revision 2.1.1 in the revision level column. 4.2 ? added ?note: rise/fall time on cpm input pins? and following note text to section 9.2, ?cpm ac timing specifications .? 4.1 ? ? inserted figure 3 and paragraph above it. ? added pci/pci-x row to input voltage characteristic and added footnote 6 to ta ble 1 . 4 ? updated section 2.1.2, ?power sequencing.? 3.5 ? updated section 2.1.2, ?power sequencing.? 3.4 ? ? updated mv ref max value in tab le 1 . ? updated mv ref max value in tab le 2 . ? added new revision level information to ta ble 6 2 . notes : ccccc is the country of assembly. this space is left blank if parts are assembled in the united states. mmmmm is the 5-digit mask number. atwlyywwa is the traceability code. fc-pbga notes : ccccc is the country of assembly. this space is left blank if parts are assembled in the united states. mmmmm is the 5-digit mask number. atwlyywwa is the traceability code. mpc85nn xpxxxxn mmmmm atwlyywwa ccccc mpcnnnntppfffcr mmmmm ccccc ywwlaz atwlyywwa ywwlaz is the assembly traceability code.
mpc8560 integrated processor hardware specifications, rev. 5 100 freescale semiconductor document revision history 3.3 ? ? updated mv ref max value in tab le 1 . ? removed figure 3. ?in tab le 4 , replaced tbd with power numbers and added footnote. ? updated specs and footnotes in ta b l e 8 . ? corrected max number for mv ref in ta b l e 1 3 . ? changed parameter ?clock cycle duration? to ?clock period? in ta ble 2 7 . ? added note 4 to t lbkhov1 and removed lale reference from t lbkhov3 in table 31 and ta b l e 3 2 . ? updated lale signal in figure 17 and figure 18 . ? modified figure 21 . ? modified figure 61 . 3.2 ? ? updated ta b l e 1 and ta ble 2 with 1.0 ghz device parameter requirements. ? added section 2.1.2, ?power sequencing ?. ? added cpm port signal drive strength to ta b l e 3 . ? updated ta b l e 4 with maximum power data. ? updated ta b l e 4 and ta ble 5 with 1 ghz speed grade information. ? updated ta b l e 6 with corrected typical i/o power numbers. ? updated ta b l e 7 note 2 lower voltage measurement point. ? replaced table 7 note 5 with spread spectrum clocking guidelines. ? added to ta b l e 8 rise and fall time information. ? added section 4.4, ?real time clock timing ?. ? added precharge information to section 6.2.2, ?ddr sdram output ac timing specifications ?. ? removed v il and v ih references from ta b l e 2 1 , table 22 , ta ble 2 3 , and ta b l e 2 4 . ? added reference level note to ta b l e 2 1 , ta ble 2 2 , ta b l e 2 3 , ta b l e 2 4 , table 25 , ta ble 2 6 , and ta b l e 2 7 . ? updated txd references to tcg in section 7.2.3.1, ?tbi transmit ac timing specifications ?. ? updated t ttkhdx value in ta b l e 2 5 . ? updated pma_rx_clk references to rx_clk in section 7.2.3.2, ?tbi receive ac timing specifications ?. ? updated rxd references to rcg in section 7.2.3.2, ?tbi receive ac timing specifications ?. ? updated ta b l e 2 7 note 2. ? corrected ta ble 2 9 f mdc and t mdc to reflect the correct minimum operating frequency. ? updated ta b l e 2 9 t mdkhdv and t mdkhdx values for clarification. ? added t lbkhkt and updated note 2 in ta ble 3 2 . ? corrected lgta timing references in figure 17 . ? updated figure 18 , figure 20 , and figure 22 . ? corrected fcc output timing reference labels in figure 24 and figure 25 . ? updated figure 50 . ?clarified ta b l e 5 4 note 5. ? updated ta b l e 5 5 and ta ble 5 6 with 1 ghz information. ? added heat sink removal discussion to section 16.2.3, ?thermal interface materials ?. ? corrected and added 1 ghz part number to ta ble 6 2 . 3.1 ? ? updated ta b l e 4 and ta ble 5 . ? added tab le 6 . ? added mck duty cycle to ta ble 1 6 . ? updated f mdc , t mdc , t mdkhdv , and t mdkhdx parameters in ta b l e 2 9 . ? added lale to t lbkhov3 parameter in ta b l e 3 1 and ta ble 3 2 , and updated figure 17 . ? corrected active level designations of some of the pins in ta b l e 5 4 . ? updated ta b l e 6 2 . table 63. document revision history (continued) rev. number date substantive change(s)
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 101 document revision history 3.0 ? ? ta b l e 1 ?corrected mii management voltage reference ? section 2.1.3?new ? ta b l e 2 ?corrected mii management voltage reference ? ta b l e 5 ?removed ?minimum? column ? ta b l e 5 ?added av dd power table ? ta b l e 8 ?new ? ta b l e 9 ?new ? ta b l e 9 ?new ? ta b l e 1 3 ?added overshoot/undershoot note. ? figure 4 ?new ? ta b l e 1 6 ?restated t mckskew1 as t mckskew , removed t mckskew2 ; added speed-specific minimum values for 333, 266, and 200 mhz; updated t ddshme values. ? updated chapter to reflect that gmii, mii and tbi can be run with 2.5v signalling. ? ta b l e 2 9 ?added mdio output valid timing ? ta b l e 3 1 ?updated t lbivkh1 , t lbixkh1 , and t lbotot . ? ta b l e 3 2 ?new ? ta b l e 2 0 , ta b l e 2 2 ?updated clock reference ? ta b l e 3 4 ?updated t tdivkh ? ta b l e 3 5 ?updated t tdkhox ? added tables and figures for cpm i 2 c ? ta b l e 4 5 ?updated t pcivkh ? section 14.1? changed minimum height from 2.22 to 3.07 and maximum from 2.76 to 3.75 ? table 54.?updated mii management voltage reference and added note 20. ? section 16.2.4.1?changed jc from 0.3 to 0.8; changed die-junction temperature from 67 to 71 ? section 17.7?added paragraph that begins ?tsec1_txd[3:0]...? 2.1 ? ? section 2.1.3?new ? ta b l e 1 6 ?added speed-specific minimum values for 333, 266, and 200 mhz ? ta b l e 3 1 ?replaced all references to tsec1_txd[6:5] to tsec2_txd[6:5] ? ta b l e 3 1 ?added t lbskew and note 3 ? ta b l e 3 1 ?added comment about rev. 2.x devices to note 5 ? section 14.1? changed minimum height from 2.22 to 3.07 and maximum from 2.76 to 3.75 ? section 16.2.4.1?changed jc from 0.3 to 0.8; changed die-junction temperature from 67 to 71 ? section 17.7?added paragraph that begins ?tsec1_txd[3:0]...? table 63. document revision history (continued) rev. number date substantive change(s)
mpc8560 integrated processor hardware specifications, rev. 5 102 freescale semiconductor document revision history 2.0 ? ? section 1.1?updated features list to coincide with latest version of the reference manual ? ta b l e 1 and ta b l e 2 ? addition of cpm to ov dd and ov in ; addition of sysclk to ov in ? ta b l e 2 ?addition of notes 1 and 2 ? ta b l e 3 ?addition of note 1 ? ta b l e 5 ?new ? section 4?new ? ta b l e 1 3 ?addition of i vref ? ta b l e 1 5 ?modified maximum values for t diskew ? ta b l e 1 6 ?added msync_out to t mckskew2 ? figure 5 ?new ? section 6.2.1?removed figure 4, ?ddr sdram input timing diagram? ? section 7.1?removed references to 2.5 v from first paragraph ? figure 8 ?new ? ta b l e 1 9 and ta ble 2 0 ?modified ?conditions? for i ih and i il ? ta b l e 2 1 ?addition of min and max for gtx_clk125 reference clock duty cycle ? ta b l e 2 5 ?addition of min and max for gtx_clk125 reference clock duty cycle ? ta b l e 2 7 ?addition of min and max for gtx_clk125 reference clock duty cycle ? figure 17 and figure 19 ?changed lsync_in to internal clock at top of each figure ? ta b l e 3 4 ?modified values for t fiivkh, t niivkh , and t tdivkh ; addition of t piivkh and t piixkh . ? ta b l e 3 5 ?modified values for t fekhox, t nikhox, t nekhox, t tdkhox ; addition of t pikhox. ? figure 16 ?new ? figure 30 ?new ? ta b l e 3 1 ?removed row for t lbkhox3 ? ta b l e 4 4 ?new (ac timing of pci-x at 66 mhz) ? ta b l e 5 4 ?addition of note 19 ? figure 61 ?addition of jumper and note at top of diagram ? ta b l e 5 6 ?changed max bus freq for 667 core to 166 ? section 16.2.1?modified first paragraph ? figure 50 ?modified ? figure 53 ?new ? ta b l e 6 0 ?modified thermal resistance data ? section 16.2.4.2?modified first and second paragraphs 1.2 ? ? section 1.1.1?updated feature list. ? section 1.2.1.1?updated notes for table 1. ? section 1.2.1.2?removed 5-v pci interface overshoot and undershoot figure. ? section 1.2.1.3?added this section to summarize impedance driver settings for various interfaces. ? section 1.4?updated rows in reset initialization timing specifications table. added a table with dll and pll timing specifications. ? section 1.5.2.2?updated note 6 of ddr sdram output ac timing specifications table. ? section 1.7?changed the minimum input low current from -600 to -15 a for the rgmii dc electrical characteristics. ? section 1.7.2?changed lcs[3:4] to tsec1_txd[6:5]. updated notes regarding lcs[3:4]. ? section 1.13.2?updated the mechanical dimensions diagram for the package. ? section 1.13.3?updated the notes for lbctl, trig_out, and asleep. corrected pin assignments for iic_sda and iic_scl. corrected reserved pin assignment of v11 to u11. v11 is actually pci_stop. ? section 1.14.1?updated the table for frequency options with respect to platform/ccb frequencies. ? section 1.14.4?edited frequency options with respect to memory bus speeds. 1.1 ? ? section 1.6.1?added symbols and note for the gtx_clk125 timing parameters. ? section 1.11.3?updated pin list table: lgpl5/lsdamux to lgpl5, la[27:29] and la[30:31] to la[27:31], trst to trst , added gbe clocking section and ec_gtx_clk125 signal. ? figure 50?updated pin 2 connection information. table 63. document revision history (continued) rev. number date substantive change(s)
mpc8560 integrated processor hardware specifications, rev. 5 freescale semiconductor 103 document revision history 1 ? initial public release table 63. document revision history (continued) rev. number date substantive change(s)
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